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vivado:getting_started_with_zynq:start [2017/09/26 20:27] – Arthur Brownvivado:getting_started_with_zynq:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
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-=== Warning === +=== Important! === 
-This page is a work in progress.+This guide is obsolete, the updated guide can be found [[:vivado:getting-started-with-ipi:start|here]].
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 +
 +{{:vivado:getting_started_with_zynq:zynq-gsg-action.png?800|}}
  
 ===== Prerequisites ===== ===== Prerequisites =====
-  * Vivado Installed +  * A Vivado installation. See [[learn:software:tutorials:vivado-install-guide:|this tutorial]]. 
-  * Familiarity with Vivado +  * Basic familiarity with Vivado. See [[:vivado:getting_started:|this tutorial]]. 
-  * Digilent Board Files+  * Digilent Board Files installed to make selection of a target board and configuration of the Zynq IP block easier. See [[software:vivado:board-files#installation|this tutorial]]. 
 +  * A Digilent Zynq Development Board to run the project on.
  
 ===== Introduction ===== ===== Introduction =====
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-==== 2. The IP Integrator ====+==== 2. Open the IP Integrator ====
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 === 2.2 === === 2.2 ===
-In the dialog box, give the block design a name and a directory location to be stored in. Make sure that //Specify source set// is set to //Design Sources//.+In the dialog box, give the block design a name. The directory location is where the block design will be stored, this can be changed, but it is recommended to leave it as //<Local to Project>//. Make sure that //Specify source set// is set to //Design Sources//.
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 === Important === === Important ===
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 +
 +==== 3. IP Integrator Tools ====
 +
 +As a general overview, Zynq designs consist of two areas, the processor, and the FPGA. The processor has some additional hardware surrounding it, and connects to other peripherals on the board that are not part of the Zynq chip. The FPGA also connects to other on board hardware. The communications protocol used to move data between the FPGA and processor, as well as between pieces of the FPGA, is called AXI.
 +
 +Each AXI peripheral programmed onto the FPGA will be assigned an area of the Zynq's memory space that will be used to address each of its control registers. Adding a simple AXI interface to a design will require the addition of two new blocks, the AXI Interconnect, which defines how the signals are routed, and the reset controller, which will connect a processor reset to the resets of each AXI block and the interface.
 +
 +Much of basic Zynq design consists of connecting different AXI peripherals to the processor, clocking them appropriately, and using them to control off-chip devices.
 +
 +With this context out of the way, many of the tools that can be used to create a design in Zynq will be described.
  
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-=== 2.3 === +=== 3.1 === 
-FIXME //Bullet-Point Overview of IPI//+The //Sources// tab, highlighted in orange in the image to the right, contains several sub-tabs, of these, //Hierarchy// and //IP Sources// are the most immediately useful. 
 + 
 +The //Hierarchy// sub-tab shows the set of sources that exist in the project. These are split up into three groups, //Design Sources// contains the block design, and beneath that, sources for all of the IP cores or other files that are included in the block design. The //Constraints// sub-tab contains Xilinx Design Constraint (XDC) files that have been added to the project. XDC files can be used to constrain ports that have been omitted from the board file. 
 + 
 +The //IP Sources// sub-tab shows the files generated when a new IP core has been added to the block design. Some annoying errors can be solved by right clicking on the block design in this screen and selecting //Reset Output Products// followed by //Generate Output Products//.
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 +{{ :vivado:getting_started_with_zynq:ipi-sources-hierarchy.png?500 |}}
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-=== 2.4 === +=== 3.2 === 
-FIXME //Bullet-Point Overview of Block Design Features//+When the //Design// tab is selected, a list of all input and output ports, IP core ports, and connections between IP cores is shown. Selecting an entry in this list will highlight that object in the block design diagram.
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 +{{ :vivado:getting_started_with_zynq:ipi-design.png?500 |}}
 </WRAP> </WRAP>
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 +
 +<WRAP group>
 +<WRAP column half>
 +=== 3.3 ===
 +The //Signals// tab allows the user to view lists of all clock and reset signals in the block design. As before, selecting an entry in either of these lists will highlight that signal in the block design diagram. This tool can be useful for figuring out where data crosses clock domains in a more complicated design.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started_with_zynq:ipi-signals.png?500 |}}
 +</WRAP>
 +</WRAP>
 +
 +<WRAP group>
 +<WRAP column half>
 +=== 3.4 ===
 +The //Board// tab displays all of the external connections that Digilent has provided as part of the board file selected as part of creating the project. This tool makes connecting these ports to a design extremely straightforward. The process of connecting one of these ports will be gone through later in this guide.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started_with_zynq:ipi-board.png?500 |}}
 +</WRAP>
 +</WRAP>
 +
 +<WRAP group>
 +<WRAP column half>
 +=== 3.5 ===
 +The //Properties// pane, found below the tabbed pane described above, shows the properties of the currently selected object. This pane is typically used to quickly view the clock frequency of a selected clock pin, or to change the name of an IP core or port.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started_with_zynq:external-interface-properties.png?500 |}}
 +</WRAP>
 +</WRAP>
 +
 +<WRAP group>
 +<WRAP column half>
 +=== 3.6 ===
 +Most of the upper right of the Vivado window is taken up by the //Diagram// pane. This pane displays a graphical rendition of the current block design. Many of the buttons in the toolbar to the left side of this pane will be described in Step 4 of this guide.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started_with_zynq:ipi-diagram.png?500 |}}
 +</WRAP>
 +</WRAP>
 +
 +<WRAP group>
 +<WRAP column half>
 +=== 3.7 ===
 +The //Address Editor// tab, contained in the same pane as the Diagram, describes the memory addresses that the processor can find each installed AXI peripheral at. Changing values in this pane is not recommended, except for advanced users. Errors in the block design validation process that refer to unmapped peripherals can be solved by right clicking anywhere in this pane and selecting //Auto-Assign Address//.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started_with_zynq:ipi-address-editor.png?500 |}}
 +</WRAP>
 +</WRAP>
 +
 +<WRAP group>
 +<WRAP column half>
 +=== 3.8 ===
 +The first tab of the pane at the bottom of the window is the //TCL Console//. This tool displays the scripted commands that Vivado is running whenever a change is made in the graphical interface. Scripts can be created to be run using this tool through the use of the 'source' command.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started_with_zynq:ipi-tcl-console.png?500 |}}
 +</WRAP>
 +</WRAP>
 +
 +<WRAP group>
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 +=== 3.9 ===
 +The //Messages// tab displays Error, Warning, Info, and Status messages created when Vivado takes different actions. These messages can also be found in the TCL Console but are presented in a relatively easy to navigate format.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started_with_zynq:ipi-messages.png?500 |}}
 +</WRAP>
 +</WRAP>
 +
 +<WRAP group>
 +<WRAP column half>
 +=== 3.10 ===
 +The //Reports// tab contains a list of different reports that Vivado generates as part of the process of generating a bitstream.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started_with_zynq:ipi-reports.png?500 |}}
 +</WRAP>
 +</WRAP>
 +
 +<WRAP group>
 +<WRAP column half>
 +=== 3.11 ===
 +By selecting //Tools -> Reports -> Report IP Status// in the toolbar at the top of the Vivado window, another tab will be added to the bottom-most pane - though this will not do anything until an IP is added to the design. This //IP Status// tab displays the versions and target devices of each IP core added to the project. If an IP is not //Up-to-date//, clicking the //Upgrade All// button will reload the IP with the most recent version, or make any updates needed to make the IP work in the version of Vivado being used.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started_with_zynq:ipi-ip-status.png?500 |}}
 +</WRAP>
 +</WRAP>
 +
 +=== 3.12 ===
 +The toolbar at the left of the //Diagram// pane has a large number of buttons that all do different things.
 +  * //Block Design Options// ({{:vivado:getting_started_with_zynq:buttons:block-design-options.png|}}) lets the user change what is displayed and how in the diagram window.
 +  * //Zoom In// ({{:vivado:getting_started_with_zynq:buttons:zoom-in.png|}}) zooms in the view, while maintaining the current center position.
 +  * //Zoom Out// ({{:vivado:getting_started_with_zynq:buttons:zoom-out.png|}}) zooms out the view, while maintaining the current center position.
 +  * //Zoom Fit// ({{:vivado:getting_started_with_zynq:buttons:zoom-fit.png|}}) zooms the view so that all blocks in the current design are shown on screen.
 +  * //Select Area// ({{:vivado:getting_started_with_zynq:buttons:select-area.png|}}) selects every block in a drawn rectangle, useful for moving groups of blocks at once.
 +  * //Fit Selection// ({{:vivado:getting_started_with_zynq:buttons:fit-selection.png|}}) zooms the view to center on the currently selected block/s.
 +  * //Search// ({{:vivado:getting_started_with_zynq:buttons:search.png|}}) launches a search through the ports and blocks in the current design.
 +  * //Add IP// ({{:vivado:getting_started_with_zynq:buttons:add-ip.png|}}) launches a search dialog to add a new IP block to the design. More on this later.
 +  * //Make External// ({{:vivado:getting_started_with_zynq:buttons:make-external.png|}}) creates an input or output port for the currently selected pin. This is useful when constraining ports with an XDC file, rather than the Digilent board file.
 +  * //Customize Block// ({{:vivado:getting_started_with_zynq:buttons:customize-block.png|}}) launches the customization dialog for the currently selected block. More on this later.
 +  * //Validate Design// ({{:vivado:getting_started_with_zynq:buttons:validate-design.png|}}) tells Vivado to look for mistakes in the block design, required before generating a bitstream. More on this later.
 +  * //IP Settings// ({{:vivado:getting_started_with_zynq:buttons:ip-settings.png|}}) opens the project settings dialog at the IP settings page. Useful for including non-standard IP repositories.
 +  * //Regenerate Layout// ({{:vivado:getting_started_with_zynq:buttons:regenerate-layout.png|}}) tells Vivado to visually clean up the block design by moving IP blocks and rerouting signals.
 +  * //Optimize Routing// ({{:vivado:getting_started_with_zynq:buttons:optimize-routing.png|}}) tells Vivado to visually clean up the block design by only rerouting signals.
 +  * //Show Interface Connections Only// ({{:vivado:getting_started_with_zynq:buttons:show-interface-connections-only.png|}}) hides clock and reset signals, only useful for highly complex designs.
 +
 +Additionally, changes to the design can be made by interacting directly with the Diagram pane's graphical interface. Objects can be moved by clicking and dragging them. Connections can be made by hovering over a port until the pencil cursor ({{:vivado:getting_started_with_zynq:pencil.png|}}) appears, then drawing a line to another port, pin, or wire.
  
 With a general understanding of the actions that can be taken in the IPI, a design can now be created. With a general understanding of the actions that can be taken in the IPI, a design can now be created.
  
-==== 3. Add the Zynq Block ====+==== 4. Add the Zynq Block ====
  
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-=== 3.1 ===+=== 4.1 ===
 The core of most IPI designs for a Zynq board is the Zynq block. Click the //Add IP// ({{:vivado:getting_started_with_zynq:buttons:add-ip.png}}) button, then search for and double click on //Zynq//. The core of most IPI designs for a Zynq board is the Zynq block. Click the //Add IP// ({{:vivado:getting_started_with_zynq:buttons:add-ip.png}}) button, then search for and double click on //Zynq//.
  
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-=== 3.2 === +=== 4.2 === 
-Before doing anything else, select //Run Block Automation// in the green tab at the top of the Block Design screen. This button launches a dialog that will add several important required connections for the processor.+Before doing anything else, select //Run Block Automation// in the green tab at the top of the block design //Diagram// pane. This button launches a dialog that will add several important required connections for the processor.
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-=== 3.3 ===+=== 4.3 ===
 The //Options// box shows what will be done when OK is clicked. FIXED_IO and DDR connections will be made external automatically. FIXED_IO represents all of the on-chip peripherals that can be enabled when configuring the Zynq block (more on this later), while the DDR connection represents the processor's connection to the on-board memory. The //Options// box shows what will be done when OK is clicked. FIXED_IO and DDR connections will be made external automatically. FIXED_IO represents all of the on-chip peripherals that can be enabled when configuring the Zynq block (more on this later), while the DDR connection represents the processor's connection to the on-board memory.
  
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-=== 3.5 ===+=== 4.4 ===
 Click //OK// to have Vivado add these connections and apply the preset. When this process is complete, the FIXED_IO and DDR connections can be seen in the block design, represented as ports directly connected to the Zynq block. Several other changes to the set of ports to and from the Zynq block can be seen. Click //OK// to have Vivado add these connections and apply the preset. When this process is complete, the FIXED_IO and DDR connections can be seen in the block design, represented as ports directly connected to the Zynq block. Several other changes to the set of ports to and from the Zynq block can be seen.
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-==== 4. Configure the Zynq Block ====+==== 5. Configure the Zynq Block ==== 
 + 
 +=== 5.1 === 
 +Additional changes can be made to the Zynq block's configuration, depending on the requirements of the project. The most common of these are the addition of a connection to the Zynq's interrupt controller, as well as the creation of additional clocks of different frequencies. Select the Zynq block by clicking on it and then clicking the //Customize Block// ({{:vivado:getting_started_with_zynq:buttons:customize-block.png|}}) button, or by double-clicking on the Zynq block.
  
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-=== 4.1 === +=== 5.2 === 
-Additional changes can be made to the Zynq block's configuration, depending on the requirements of the project. The most common of these are the addition of a connection to the Zynq's interrupt controller, as well as the creation of additional clocks of different frequencies.+The page that is open when the Re-Customize dialog is launched for the Zynq block is called //Zynq Block Design//. This page displays the hardware used by the Zynq chip. Note the //I/O Peripherals// block, the check-marks display what peripherals are currently enabled. All of the information shown in this screen is available in lists in the other pages.
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 +{{ :vivado:getting_started_with_zynq:zynq-config:zynq-block-design.png?500 |}}
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-=== 4.2 === +=== 5.3 === 
-FIXME //Overview Tabs//+The //PS-PL Configuration// page allows the user to customize how the processor will communicate with the FPGA. There are several settings of particular note here. 
 +  * The UART baud rate settings found in the //General// drop-down are used to change the baud rate that the Zynq communicates with a computer serial port at. 
 +  * //GP/HP Slave AXI Interfaces// (General Purpose / High Performance) are used when an AXI peripheral requires control over a memory interface, this can be seen in Digilent's HDMI and Audio DMA demo projects. 
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 +{{ :vivado:getting_started_with_zynq:zynq-config:ps-pl-configuration.png?500 |}}
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-=== 4.3 === +=== 5.4 === 
-FIXME //Expanded Overviews for tabs that require more than one image (interrupt, clocks, enable HP0/GP0, etc.)//+The //Peripheral I/O Pins// page allows the user to enable or disable a large number of different hardware peripherals that cannot be controlled directly from the FPGA. As an example, enabling GPIO MIO allows the user to control LED 4 (LD4/MIO7) on the Zybo board.
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 +{{ :vivado:getting_started_with_zynq:zynq-config:peripheral-io-pins.png?500 |}}
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-=== 4.4 === +=== 5.5 === 
-Since the target design for this guide requires no major changes to the Zynq block's configuration, select //Cancel// or //close// the dialog. Changes are not saved except when //Apply// or //Finish// is selected.+The //MIO Configuration// page shares much of its information with Peripheral I/O Pins, and allows the user to view this in a list, rather than the graphical table format.
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 +{{ :vivado:getting_started_with_zynq:zynq-config:mio-configuration.png?500 |}}
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-==== 5. Add Peripherals ====+<WRAP group> 
 +<WRAP column half> 
 +=== 5.6 === 
 +The //Clock Configuration// page contains important settings that allow the user to provide additional clocks at different speeds to the FPGA, as well as tweaking the clock frequencies of several IO Peripherals. Take note of the //PL Fabric Clocks// drop-down, checking a box for one of FCLK_CLK1-3 will provide an additional clock output from the Zynq block, at or near the provided //Requested Frequency//. 
 +</WRAP> 
 +<WRAP column half> 
 +{{ :vivado:getting_started_with_zynq:zynq-config:clock-configuration.png?500 |}} 
 +</WRAP> 
 +</WRAP> 
 + 
 +<WRAP group> 
 +<WRAP column half> 
 +=== 5.7 === 
 +The //DDR Configuration// page contains a large number of settings about the DDR chip connected to the Zynq chip. This page alone is the reason to use the board preset brought in from Digilent's board file. Changing these settings is //not recommended//. 
 +</WRAP> 
 +<WRAP column half> 
 +{{ :vivado:getting_started_with_zynq:zynq-config:ddr-configuration.png?500 |}} 
 +</WRAP> 
 +</WRAP> 
 + 
 +<WRAP group> 
 +<WRAP column half> 
 +=== 5.8 === 
 +The //Interrupts// page is another extremely useful one. To use any interrupts with the FPGA, the //Fabric Interrupts// checkbox must be checked. Many AXI IP cores can be configured to generate an interrupt on some trigger, for instance AXI GPIO cores can be set up to trigger an interrupt whenever an input changes. Checking the //IRQ_F2P// box in the //PL-PS Interrupt Ports// drop-down creates a new input port on the Zynq block which can be connected to up to sixteen individual interrupt pins via a Concat (concatenation) IP core. To use interrupts, the 'xscugic' driver for the generic interrupt controller found in the Zynq hardware must be used. 
 + 
 +Additionally, interrupts generated by hardware peripherals connected using the Peripheral I/O Pins or MIO Configuration pages can be provided to the FPGA using the fields in the //PS-PL Interrupt Ports// drop-down. 
 +</WRAP> 
 +<WRAP column half> 
 +{{ :vivado:getting_started_with_zynq:zynq-config:interrupts.png?500 |}} 
 +</WRAP> 
 +</WRAP> 
 + 
 +Since the target design for this guide requires no major changes to the Zynq block's configuration, select //Cancel// or click the 'X' to close the dialog. Changes are not saved except when //Apply// or //Finish// is selected. 
 + 
 +==== 6. Add Peripherals ====
  
 In order to use the Zynq processor to control the board's RGB LEDs and Buttons, an AXI GPIO IP core needs to be added to the block design. In order to use the Zynq processor to control the board's RGB LEDs and Buttons, an AXI GPIO IP core needs to be added to the block design.
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-=== 5.1 === +=== 6.1 === 
-In the //Board// tab to the left of the window, right click on //RGB LEDs// and select //Connect Board Component//. If the board does not have RGB LEDs, use the normal LEDs instead.+In the //Board// tab to the left of the diagram pane, right click on //RGB LEDs// and select //Connect Board Component//. If the board does not have RGB LEDs, use the normal LEDs instead.
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-=== 5.2 ===+=== 6.2 ===
 This launches a dialog that provides the different IP blocks that this port can be connected to. Select //AXI GPIO//. This launches a dialog that provides the different IP blocks that this port can be connected to. Select //AXI GPIO//.
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-=== 5.3 === +=== 6.3 === 
-This will place a general purpose input/output controller into the block design. Required configuration settings for the size of the GPIO channel will already be done, but additional options, like creating an interrupt port, or adding a second channel can be enabled by configuring the IP. The IP can be customized by double clicking on it, or by selecting it and clicking the //Customize Block// button ({{:vivado:getting_started_with_zynq:buttons:customize-block.png|}}).+This will place a general purpose input/output (GPIO) controller into the block design. Required configuration settings for the size of the GPIO channel will already be done, but additional options, like creating an interrupt port, or adding a second channel can be enabled by configuring the IP. The IP can be customized by double clicking on it, or by selecting it and clicking the //Customize Block// button ({{:vivado:getting_started_with_zynq:buttons:customize-block.png|}}).
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-=== 5.4 ===+=== 6.4 ===
 Since an AXI GPIO controller with a free channel - each block can control up to two different peripherals - already exists, when making a connection with the //User Buttons// port, the option of connecting the port to the second channel of axi_gpio_0 will be available. Select this option from the menu, then continue. Since an AXI GPIO controller with a free channel - each block can control up to two different peripherals - already exists, when making a connection with the //User Buttons// port, the option of connecting the port to the second channel of axi_gpio_0 will be available. Select this option from the menu, then continue.
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-==== 6. Connect the AXI Blocks to the Zynq Block ====+==== 7. Connect the AXI Blocks to the Zynq Block ====
  
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-=== 6.1 ===+=== 7.1 ===
 At this point, the green bar at the top of the screen will have reappeared, this time saying //Run Connection Automation//. Click this. At this point, the green bar at the top of the screen will have reappeared, this time saying //Run Connection Automation//. Click this.
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-vivado:getting_started_with_zynq:buttons:run-connection.png?500 |}}+{{ :vivado:getting_started_with_zynq:buttons:run-connection.png?500 |}}
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-=== 6.2 === +=== 7.2 === 
-Make sure that the axi_gpio_0 block is checked in the menu to the left. Several options are present here, including the clock that the AXI Interface will run off of.+Make sure that the axi_gpio_0 block is checked in the menu to the left. Several options are present here, including the a drop-down to select the clock that the AXI Interface will run off of - keep this field as //Auto// to let Vivado pick.
  
 Click //Finish// to generate the AXI connection and its related blocks. Click //Finish// to generate the AXI connection and its related blocks.
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 </WRAP> </WRAP>
  
-AXI is the communications protocol that is used by the Zynq processor to communicate with each of the peripheral controllers in the design. Each peripheral will be assigned an area of the Zynq's memory space that will be used to address each of its controller's registers. Adding a simple AXI interface to a design will require the addition of two new blocks, the AXI Interconnect, which defines how the signals are routed, and the reset controller, which will connect a processor reset to the resets of each AXI block and the interface. +==== 8. Generate the Bitstream ====
- +
-==== 7. Generate the Bitstream ====+
  
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 7.1 ===+=== 8.1 ===
 At this point, a complete design has been created. Click the //Validate Design// button ({{:vivado:getting_started_with_zynq:buttons:validate-design.png|}}) to have Vivado confirm that everything looks good. At this point, a complete design has been created. Click the //Validate Design// button ({{:vivado:getting_started_with_zynq:buttons:validate-design.png|}}) to have Vivado confirm that everything looks good.
  
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 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 7.2 ===+=== 8.2 ===
 The last thing that needs to be done before generating a bitstream is to create a top module file. This file will take the block design and interpret it into a hardware design language so that the synthesis and implementation tools can work properly. Right click on the block design in the //Sources// tab in the pane to the left of the //Block Design// pane - this pane likely has the //Board// tab currently selected. The last thing that needs to be done before generating a bitstream is to create a top module file. This file will take the block design and interpret it into a hardware design language so that the synthesis and implementation tools can work properly. Right click on the block design in the //Sources// tab in the pane to the left of the //Block Design// pane - this pane likely has the //Board// tab currently selected.
  
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 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 7.3 === +=== 8.3 === 
-With a validated design and a top module, a bitstream can now be generated. The Getting Started with Vivado guide explains this process in a little more detail, but for now, click the //Generate Bitstream// button in the //Flow Navigator//.+With a validated design and a top module, a bitstream can now be generated. The [[:vivado:getting_started:|Getting Started with Vivado]] guide explains this process in a little more detail, but for now, click the //Generate Bitstream// button in the //Flow Navigator//.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
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 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 7.4 ===+=== 8.4 ===
 The Launch Runs dialog that pops up has several options to choose between. Select //Launch runs on local host// to actually generate the bitstream now. The other option is to //Generate scripts only//, which will not generate a bitstream, but rather the scripts required to generate the bitstream on a different machine. The //Number of jobs// field allows the user to change how much of the resources of the computer Vivado is running on will be used. This process can take some time for complex designs, so it is recommended to devote as much of the resources as possible (typically by selecting '8'). The Launch Runs dialog that pops up has several options to choose between. Select //Launch runs on local host// to actually generate the bitstream now. The other option is to //Generate scripts only//, which will not generate a bitstream, but rather the scripts required to generate the bitstream on a different machine. The //Number of jobs// field allows the user to change how much of the resources of the computer Vivado is running on will be used. This process can take some time for complex designs, so it is recommended to devote as much of the resources as possible (typically by selecting '8').
 </WRAP> </WRAP>
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 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 7.5 ===+=== 8.5 ===
 In the next dialog, No Implementation Results Available, Vivado will ask whether to run Synthesis and Implementation. These steps are required to generate a bitstream, so click //Yes//. In the next dialog, No Implementation Results Available, Vivado will ask whether to run Synthesis and Implementation. These steps are required to generate a bitstream, so click //Yes//.
 </WRAP> </WRAP>
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 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 7.6 ===+=== 8.6 ===
 Once the bitstream is generated, which may take a little while, Vivado will ask what to do next. None of the available options are required for this guide, so click //Cancel//. Once the bitstream is generated, which may take a little while, Vivado will ask what to do next. None of the available options are required for this guide, so click //Cancel//.
 </WRAP> </WRAP>
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 </WRAP> </WRAP>
  
-==== 8. Launch Vivado SDK ====+==== 9. Launch Vivado SDK ====
  
 Before Vivado SDK can be launched, it needs to be provided with a hardware handoff file, containing the bitstream and various other information about the peripherals installed in the design. Before Vivado SDK can be launched, it needs to be provided with a hardware handoff file, containing the bitstream and various other information about the peripherals installed in the design.
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 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 8.1 === +=== 9.1 === 
-In the //File// dropdown, select //Export// then //Export to SDK//.+In the //File// drop-down, select //Export// then //Export to SDK//.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
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 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 8.2 ===+=== 9.2 ===
 Make sure that the //Include Bitstream// box is checked, so that the FPGA can be programmed from Vivado SDK. The //Export Location// is //<Local To Project>// by default. This means that Vivado will create a new directory in the project directory called '<project name>.sdk' where the hardware handoff file - named '<HDL wrapper name>.hdf' - can be found. If a different location is chosen for the hardware handoff file, make sure to remember where it is. Make sure that the //Include Bitstream// box is checked, so that the FPGA can be programmed from Vivado SDK. The //Export Location// is //<Local To Project>// by default. This means that Vivado will create a new directory in the project directory called '<project name>.sdk' where the hardware handoff file - named '<HDL wrapper name>.hdf' - can be found. If a different location is chosen for the hardware handoff file, make sure to remember where it is.
 <WRAP center round important> <WRAP center round important>
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 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 8.3 === +=== 9.3 === 
-Just below //Export// in the //File// dropdown, select //Launch SDK//.+Just below //Export// in the //File// drop-down, select //Launch SDK//.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
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 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 8.4 ===+=== 9.4 ===
 The dialog that pops up will tell Vivado where to find the exported files, as well as where to create the SDK workspace. Make sure to set //Exported Location// to the location chosen earlier. The //Workspace// field is //<Local To Project>// by default. This means that Vivado will use a directory in the project directory called '<project name>.sdk' to store the sources and projects created in Vivado SDK. If this directory does not exist, it will be created. This location can be changed if somewhere else is desired, but it is recommended to leave it as is. The dialog that pops up will tell Vivado where to find the exported files, as well as where to create the SDK workspace. Make sure to set //Exported Location// to the location chosen earlier. The //Workspace// field is //<Local To Project>// by default. This means that Vivado will use a directory in the project directory called '<project name>.sdk' to store the sources and projects created in Vivado SDK. If this directory does not exist, it will be created. This location can be changed if somewhere else is desired, but it is recommended to leave it as is.
 <WRAP center round important> <WRAP center round important>
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 </WRAP> </WRAP>
  
-==== 9. Create a New C Project ====+==== 10. Create a New C Project ====
  
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 9.1 ===+=== 10.1 ===
 Vivado SDK will now launch, and will import the hardware definition, creating a workspace containing only a hw_platform project. This project contains the files exported from Vivado. There are only a few relevant panes to this guide. Vivado SDK will now launch, and will import the hardware definition, creating a workspace containing only a hw_platform project. This project contains the files exported from Vivado. There are only a few relevant panes to this guide.
   * The //Project Explorer//, found to the left hand side of the window, displays all projects imported into the workspace, each of which can be expanded to view the sources, scripts, and other files that they contain.   * The //Project Explorer//, found to the left hand side of the window, displays all projects imported into the workspace, each of which can be expanded to view the sources, scripts, and other files that they contain.
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 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 9.1 ===+=== 10.2 ===
 In order to create a project to store C source code, click //File// in the top toolbar, followed by //New > Application Project//. In order to create a project to store C source code, click //File// in the top toolbar, followed by //New > Application Project//.
 </WRAP> </WRAP>
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 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 9.2 === +=== 10.3 ===
-</WRAP>+
 In the New Project dialog, give the project a name, and make sure that //C// is selected as the //Language// in the //Target Software// box. In the New Project dialog, give the project a name, and make sure that //C// is selected as the //Language// in the //Target Software// box.
 <WRAP center round important> <WRAP center round important>
 === Important === === Important ===
-Do NOT use spaces in the export location path. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]].+Do NOT use spaces in the project name. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]].
 </WRAP> </WRAP>
 Click //Next// to continue. Click //Next// to continue.
 +</WRAP>
 <WRAP column half> <WRAP column half>
 {{ :vivado:getting_started_with_zynq:sdk-dialog-new-project.png?500 |}} {{ :vivado:getting_started_with_zynq:sdk-dialog-new-project.png?500 |}}
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 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 9.3 ===+=== 10.4 ===
 From the list of Available Templates, select //Empty Application//, then click //Finish//. From the list of Available Templates, select //Empty Application//, then click //Finish//.
 </WRAP> </WRAP>
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 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 9.4 ===+=== 10.5 ===
 Expand the newly created project - not its board support package - then expand the 'src' folder. Right-click on the 'src' folder and select //New > Source File// from the menu. Expand the newly created project - not its board support package - then expand the 'src' folder. Right-click on the 'src' folder and select //New > Source File// from the menu.
 </WRAP> </WRAP>
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 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 9.5 ===+=== 10.6 ===
 Name the new source file 'main.c', then click //Finish//. Name the new source file 'main.c', then click //Finish//.
 </WRAP> </WRAP>
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 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 9.6 ===+=== 10.7 ===
 The new main file will now open in the file view pane. Copy-Paste the code to the right into this file, then hit //Ctrl-S// to save the file and build the project. The new main file will now open in the file view pane. Copy-Paste the code to the right into this file, then hit //Ctrl-S// to save the file and build the project.
 </WRAP> </WRAP>
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 </WRAP> </WRAP>
  
-==== 10. Program and Run the Design ====+==== 11. Program and Run the Design ====
  
 The next step is to program the bit file onto the FPGA and run the C source on the processor. The next step is to program the bit file onto the FPGA and run the C source on the processor.
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 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 10.1 ===+=== 11.1 ===
 From the top toolbar, select //Xilinx Tools//, then //Program FPGA//. From the top toolbar, select //Xilinx Tools//, then //Program FPGA//.
 </WRAP> </WRAP>
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 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 10.2 === +=== 11.2 === 
 +Leave all of the settings in the Program FPGA dialog as they are, then click //Program//. This only programs the FPGA, not the processor, so that is next.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
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 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 10.3 ===+=== 11.3 === 
 +Right click on the application project in the //Project Explorer//, then select //Run As > Launch on Hardware (System Debugger)//.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>