Getting Started with Zynq and the Vivado IP Integrator

1.1

With Vivado freshly opened, click Create New Project.

1.2

The first page of this wizard summarizes the steps involved in creating a project. Click Next.

1.3

The first step is to set the name of the project. Vivado will use this name when generating its folder structure.

Click Next to continue.

1.4

At the Select Project Type screen, choose RTL Project and check the Do not specify sources at this time box. Advanced users may want to use the other options on this screen, but they will not be covered in this guide.

Click Next to continue.

1.5

This screen selects the part targeted by the project. If you haven't yet installed Digilent's Board Files, return to the prerequisites section of this guide and follow the link to that tutorial, Vivado will then need to be restarted to load these files properly. Select the Boards tab, then find and select your board from the list. Click Next.

1.6

This screen summarizes selections chosen in the previous screens. Click Next to finish opening the new project.

2.1

A more complete run-down of the standard Vivado work-flow can be found in Digilent's Getting Started with Vivado tutorial. This guide will be exclusively using the IP Integrator tool, which can be opened from the Flow Navigator on the right side of the window. Expand the IP Integrator tab and select Create Block Design.

2.2

In the dialog box, give the block design a name and a directory location to be stored in. Make sure that Specify source set is set to Design Sources.

Click OK to create the block design and open IPI.

2.3

Bullet-Point Overview of IPI

2.4

Bullet-Point Overview of Block Design Features

3.1

The core of most IPI designs for a Zynq board is the Zynq block. Click the Add IP () button, then search for and double click on Zynq.

The block that is added represents the Zynq ARM processor and its available connections to other hardware on the Zynq chip, including the FPGA.

3.2

Before doing anything else, select Run Block Automation in the green tab at the top of the Block Design screen. This button launches a dialog that will add several important required connections for the processor.

3.3

The Options box shows what will be done when OK is clicked. FIXED_IO and DDR connections will be made external automatically. FIXED_IO represents all of the on-chip peripherals that can be enabled when configuring the Zynq block (more on this later), while the DDR connection represents the processor's connection to the on-board memory.

Make sure that Apply Board Preset is checked, so that various important settings like DDR timings will be imported from the selected target board file. Applying these settings manually is extremely tedious and easy to get wrong.

Cross Trigger In/Out are outside of the scope of this guide, so leave them Disabled.

3.5

Click OK to have Vivado add these connections and apply the preset. When this process is complete, the FIXED_IO and DDR connections can be seen in the block design, represented as ports directly connected to the Zynq block. Several other changes to the set of ports to and from the Zynq block can be seen.

4.1

Additional changes can be made to the Zynq block's configuration, depending on the requirements of the project. The most common of these are the addition of a connection to the Zynq's interrupt controller, as well as the creation of additional clocks of different frequencies.

4.2

Overview Tabs

4.3

Expanded Overviews for tabs that require more than one image (interrupt, clocks, enable HP0/GP0, etc.)

4.4

Since the target design for this guide requires no major changes to the Zynq block's configuration, select Cancel or close the dialog. Changes are not saved except when Apply or Finish is selected.

5.1

In the Board tab to the left of the window, right click on RGB LEDs and select Connect Board Component. If the board does not have RGB LEDs, use the normal LEDs instead.

5.2

This launches a dialog that provides the different IP blocks that this port can be connected to. Select AXI GPIO.

5.3

This will place a general purpose input/output controller into the block design. Required configuration settings for the size of the GPIO channel will already be done, but additional options, like creating an interrupt port, or adding a second channel can be enabled by configuring the IP. The IP can be customized by double clicking on it, or by selecting it and clicking the Customize Block button ().

5.4

Since an AXI GPIO controller with a free channel - each block can control up to two different peripherals - already exists, when making a connection with the User Buttons port, the option of connecting the port to the second channel of axi_gpio_0 will be available. Select this option from the menu, then continue.

6.1

At this point, the green bar at the top of the screen will have reappeared, this time saying Run Connection Automation. Click this.

vivado:getting_started_with_zynq:buttons:run-connection.png?500 |}}

6.2

Make sure that the axi_gpio_0 block is checked in the menu to the left. Several options are present here, including the clock that the AXI Interface will run off of.

Click Finish to generate the AXI connection and its related blocks.

At this point the block diagram may have become very messy, the Regenerate Layout () button can be clicked to have Vivado place the blocks and signals in more sensible locations.

7.1

At this point, a complete design has been created. Click the Validate Design button () to have Vivado confirm that everything looks good.

Click OK to continue.

7.2

The last thing that needs to be done before generating a bitstream is to create a top module file. This file will take the block design and interpret it into a hardware design language so that the synthesis and implementation tools can work properly. Right click on the block design in the Sources tab in the pane to the left of the Block Design pane - this pane likely has the Board tab currently selected.

In the right-click menu, select Create HDL Wrapper. In the confirmation dialog that pops up, make sure that Let Vivado manage wrapper and auto-update is selected in the options list. If manual changes need to be made to the wrapper file, the other option here can be selected, but it is not recommended except for advanced users. Click OK to have Vivado finish making the wrapper file.

7.3

With a validated design and a top module, a bitstream can now be generated. The Getting Started with Vivado guide explains this process in a little more detail, but for now, click the Generate Bitstream button in the Flow Navigator.

7.4

The Launch Runs dialog that pops up has several options to choose between. Select Launch runs on local host to actually generate the bitstream now. The other option is to Generate scripts only, which will not generate a bitstream, but rather the scripts required to generate the bitstream on a different machine. The Number of jobs field allows the user to change how much of the resources of the computer Vivado is running on will be used. This process can take some time for complex designs, so it is recommended to devote as much of the resources as possible (typically by selecting '8').

7.5

In the next dialog, No Implementation Results Available, Vivado will ask whether to run Synthesis and Implementation. These steps are required to generate a bitstream, so click Yes.

7.6

Once the bitstream is generated, which may take a little while, Vivado will ask what to do next. None of the available options are required for this guide, so click Cancel.

8.1

In the File dropdown, select Export then Export to SDK.

8.2

Make sure that the Include Bitstream box is checked, so that the FPGA can be programmed from Vivado SDK. The Export Location is <Local To Project> by default. This means that Vivado will create a new directory in the project directory called '<project name>.sdk' where the hardware handoff file - named '<HDL wrapper name>.hdf' - can be found. If a different location is chosen for the hardware handoff file, make sure to remember where it is.

Click OK to continue.

8.3

Just below Export in the File dropdown, select Launch SDK.

8.4

The dialog that pops up will tell Vivado where to find the exported files, as well as where to create the SDK workspace. Make sure to set Exported Location to the location chosen earlier. The Workspace field is <Local To Project> by default. This means that Vivado will use a directory in the project directory called '<project name>.sdk' to store the sources and projects created in Vivado SDK. If this directory does not exist, it will be created. This location can be changed if somewhere else is desired, but it is recommended to leave it as is.

Click OK to continue.

9.1

Vivado SDK will now launch, and will import the hardware definition, creating a workspace containing only a hw_platform project. This project contains the files exported from Vivado. There are only a few relevant panes to this guide.

• The Project Explorer, found to the left hand side of the window, displays all projects imported into the workspace, each of which can be expanded to view the sources, scripts, and other files that they contain.
• The File View, directly in the center of the window, displays currently opened files. Upon launch of SDK, an overview of the hardware platform exported from Vivado is displayed. Note the AXI GPIO cell contained in the Address Map, and the corresponding entry in the list of IP blocks.

9.1

In order to create a project to store C source code, click File in the top toolbar, followed by New > Application Project.

9.2

9.3

From the list of Available Templates, select Empty Application, then click Finish.

9.4

Expand the newly created project - not its board support package - then expand the 'src' folder. Right-click on the 'src' folder and select New > Source File from the menu.

9.5

Name the new source file 'main.c', then click Finish.

9.6

The new main file will now open in the file view pane. Copy-Paste the code to the right into this file, then hit Ctrl-S to save the file and build the project.

#include "xgpio.h"
#include "xparameters.h"
 
int main() {
    XGpio gpio;
    u32 button_data;
 
    // look up the settings for the AXI GPIO IP core and initialize a driver for it
    XGpio_Initialize(&gpio, XPAR_AXI_GPIO_0_DEVICE_ID);
 
    // set LED channel (1) tristates to all output
    XGpio_SetDataDirection(&gpio, 1, 0b0000);
    //set Button channel (2) tristates to all input
    XGpio_SetDataDirection(&gpio, 2, 0b1111);
 
    while (1) {
    	//capture button data
    	button_data = XGpio_DiscreteRead(&gpio, 2);
 
    	//if any button is pressed, set all LED pins high, else turn LEDs off
    	if (button_data != 0) {
    		XGpio_DiscreteWrite(&gpio, 1, 0b1111);
    	}
    	else {
    		XGpio_DiscreteWrite(&gpio, 1, 0b0000);
    	}
    }
}

10.1

From the top toolbar, select Xilinx Tools, then Program FPGA.

10.2

10.3