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| programmable-logic:cmod-s6:reference-manual [2022/02/15 12:25] – Martha | programmable-logic:cmod-s6:reference-manual [2022/10/04 04:38] (current) – external edit 127.0.0.1 | ||
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| The Spartan 6 LX4 FPGA includes 3,840 6-LUT logic cells, 4,800 flip-flops, 216Kb of block RAM, 8 DSP slices, and two clock management tiles, each with two DCMs and one PLL. The fabric can support internal clock speeds above | The Spartan 6 LX4 FPGA includes 3,840 6-LUT logic cells, 4,800 flip-flops, 216Kb of block RAM, 8 DSP slices, and two clock management tiles, each with two DCMs and one PLL. The fabric can support internal clock speeds above | ||
| 400MHz, allowing the Cmod S6 to host high-speed or complex designs. Please see the Spartan 6 user manual | 400MHz, allowing the Cmod S6 to host high-speed or complex designs. Please see the Spartan 6 user manual | ||
| - | available at [[http:// | + | available at [[https://www.xilinx.com|www.xilinx.com]] for more detailed information. |
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