Arty Z7 HDMI Output Demo

The Arty Z7 HDMI Out project demonstrates the usage of the HDMI out port on the Arty Z7 board. There are two projects, one for each variant of the board: Arty Z7-10 and Arty Z7-20. The behavior is as follows:

• Frames stream out through the HDMI OUT port.
• A UART interface is available to configure what is output through HDMI.
• There are 3 display frame buffers that the user can choose to display.

• Arty Z7 (-10 or -20) with a MicroUSB Programming Cable
• Vivado and Vitis installations compatible with the latest release of this demo (2020.1)
  • See Installing Vivado, Vitis, and Digilent Board Files for installation instructions.
• Serial Terminal application to receive messages printed by the demo
  • See Installing and Using a Terminal Emulator (Redirect) for more information.
• HDMI-capable Monitor
• 1 HDMI Cable

First and foremost, releases - consisting of a set of files for download - are only compatible with a specific version of the Xilinx tools, as specified in the name of the release (referred to as a release tag). In addition, releases are only compatible with the specified variant of the board. For example, a release tagged “20/DMA/2020.1” for the Zybo Z7 is only to be used with the -20 variant of the board and Xilinx tools (Vivado and Vitis) version 2020.1.

The latest release version for this demo is highlighted in green.

Note: Releases for FPGA demos from before 2020.1 used a different git structure, and used a different release tag naming scheme.

Note for Advanced Users: All demos for the Arty Z7 are provided through the Arty-Z7 repository on Github. Further documentation on the structure of this repository can be found on this wiki's Digilent FPGA Demo Git Repositories (Redirect) page.

Instructions on the use of the latest release can be found in this dropdown:

Using the Latest Release

This page has been moved, the new location is Using a Digilent FPGA Github Demo's Releases (2020.1).

Set up the Arty Z7

Plug the Arty Z7 into the computer via the microUSB programming cable.

Plug one end of the HDMI cable into a video monitor and the other into the Arty Z7 HDMI out port.

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This page has been moved, the new location is Using a Digilent FPGA Github Demo's Releases (2020.1).

At this point, the demo is now running on your board. Refer to the Description section of this document for more information on what it does. The HDMI Display Options section, below, presents each of the commands that can be sent over serial to the application in order to configure it or have it perform some operation.

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Additional steps beyond here present how you can use the other archive provided in the release, containing the hardware project, to rebuild the Vivado project, and use a newly exported XSA file to update the platform in Vitis.

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This page has been moved, the new location is Using a Digilent FPGA Github Demo's Releases (2020.1).

Changes the resolution used for HDMI Output.

Changes the VDMA framebuffer used for the video output. Each framebuffer represents a different block of DDR memory which can be modified by the processor and read by the VDMA to repeatedly stream the frame out through the HDMI OUT port.

Stores one of two test test patterns (blended colors or vertical color bars) into the output buffer, to be displayed immediately. Note that if video input is streaming into the same buffer, the test pattern may be immediately overwritten.

Also to note, if the resolution of the video output is later changed, the video data is cropped or padded to fit the screen. This cropping and padding does not affect the actual stored memory, as it is a result of how the VDMA indexes the framebuffer's region of DDR memory. Storing a new test pattern does not affect the memory in the framebuffer outside of the current display area - including areas that would not be displayed with the current output resolution.

Iterates through each pixel in the current framebuffer, and inverts the colors. When choosing option 6 instead of 5, the current framebuffer is copied to another framebuffer while doing the inversion, switching to the second buffer after the operation is complete. In this case, the original framebuffer is not modified, and the entire display updates only once the entire operation has been completed.

All materials related to the use of the Arty Z7 can be found on its Resource Center.

For a walkthrough of the process of creating a simple baremetal software project in Vivado and Vitis, see Getting Started with Vivado IP Integrator and Vitis (Redirect). Information on important parts of the GUIs, and indirect discussion of the steps required to modify, rebuild, and run this demo in hardware can also be found here.

For technical support, please visit the FPGA section of the Digilent Forum.

{{tag>project arty-z7}}