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learn:fundamentals:digital-logic:verilog-hdl-the-first-example:start [2016/08/09 16:45] – created Marthalearn:fundamentals:digital-logic:verilog-hdl-the-first-example:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 </code> </code>
  
 +Indexing a bus in Verilog is similar to indexing an array in the C language. For example, if we want to index the second bit of sw bus declared above, we will use sw[1].
 +
 +===== Assign Statement =====
 +The assign statement in the example above assigns the signal value on the net “sw” to the net “led”. In implementation, it creates a wire that connects the input port sw to the output port LED.
 +
 +An assign statement can also be used to assign one signal of a bus to one signal of another bus. For example, if we declared sw as an 8-bit wide bus and LED as an 8-bit wide bus, and we want to use second switch to control fourth LED, the code will be:
 +
 +<code vhdl>
 +module led_sw(
 +output [7:0] led,
 +input [7:0] sw
 +);
 +assign led[3] = sw[1];
 +...
 +endmodule
 +</code>
 +
 +===== Constants =====
 +You can also assign a constant number to a signal or a bus to tie them to either logic '1' (VDD) or logic '0' (GND). The basic syntax for a constant number in Verilog is:
 +
 +**<Width in bits>'<base letter><number>**\\
 +
 +For example:
 +^ Constant in Verilog  ^ Explanation              ^ Value in Binary           ^
 +| 12'h123              | 12 bits Hexadecimal 123  | 0001 0010 0011            |
 +| 20'd44               | 20 bits Decimal 44       | 0000 0000 0000 0010 1100  |
 +| 4'b1010              | 4 bits Binary 1010       | 1010                      |
 +
 +
 +To tie a signal or a bus to constant, we can use assign statement as well. For example, if we are going to tie an 8-bit bus “seg” to ground, we will write:
 +
 +<code vhdl>
 +module top (
 +...
 +output [7:0] seg,
 +...
 +);
 +assign seg = 8'd0;
 +...
 +endmodule
 +</code>
 +
 +----
 +==== Important Ideas ====
 +  * Module in Verilog HDL acts like the bounding box in circuit schematic.
 +  * Bus is a group of signals (wires).
 +  * Assign statement passes the value of a signal/bus to another signal/bus.
 +  * Constant in Verilog HDL is presented in form of **<Width in bits>'<base letter><number>**
 +
 +{{tag>learn fundamentals digital-logic verilog vhdl hdl verilog-example}}