XDC Formatting Info

This Guide is to standardize our format for XDCs. All Digilent XDCs should follow this format to help ease the transfer of projects between boards.

All the XDCs should use the one line format which can be generated through EAGLE. The basic format is below. The only thing that the below sections will show is how to properly fill the (signal name) section. The other portions need to come from the board schematic.

#set_property -dict { PACKAGE_PIN X   IOSTANDARD X } [get_ports { (signal name) }]; #(fpga port) Sch=(schematic name)

All switches should designated by a lower case sw as seen below. The ports should be numbered from 0 to NUMBER_OF_SWITCHES. This will let the user use the name as a bus. Example of 8 LEDs

# Switches
[get_ports { sw[0] }];
[get_ports { sw[1] }];
[get_ports { sw[2] }];
[get_ports { sw[3] }];
[get_ports { sw[4] }];
[get_ports { sw[5] }];
[get_ports { sw[6] }];
[get_ports { sw[7] }];

All LEDs should designated by a lower case led as seen below. The ports should be numbered from 0 to NUMBER_OF_LEDs. This will let the user use the name as a bus. Example of 8 LEDs

# LEDs
[get_ports { led[0] }];
[get_ports { led[1] }];
[get_ports { led[2] }];
[get_ports { led[3] }];
[get_ports { led[4] }];
[get_ports { led[5] }];
[get_ports { led[6] }];
[get_ports { led[7] }];

All LEDs should be designated by a lower case “btn” then the indicator of the position of the button

# Buttons
[get_ports { btnc }];
[get_ports { btnd }];
[get_ports { btnl }];
[get_ports { btnr }];
[get_ports { btnu }];

All LEDs should be designated by a lower case “btn” then the indicator of the position of the button

# Buttons
[get_ports { btn[0] }];
[get_ports { btn[1] }];
[get_ports { btn[2] }];
[get_ports { btn[3] }];

The active high reset button (if applicable) will be named “cpu_resetn”

[get_ports { cpu_resetn }];

The pmod headers will be designated by jx where x is the letter specifying which header is used. The ports should be numbered from 0 to 7. This will let the user use the name as a bus.

# Pmod header JX
[get_ports { jx[0] }];
[get_ports { jx[1] }];
[get_ports { jx[2] }];
[get_ports { jx[3] }];
[get_ports { jx[4] }];
[get_ports { jx[5] }];
[get_ports { jx[6] }];
[get_ports { jx[7] }];

The XADC pmod headers will be designated by xa_n or xa_p and numbered from 0 - 3 to be used as a bus.

# XADC Header 
[get_ports { xa_n[0] }];
[get_ports { xa_p[0] }];
[get_ports { xa_n[1] }];
[get_ports { xa_p[1] }];
[get_ports { xa_n[2] }];
[get_ports { xa_p[2] }];
[get_ports { xa_n[3] }];
[get_ports { xa_p[3] }];

The two UART signals will be named as follows

[get_ports { uart_rx_out }];
[get_ports { uart_tx_in }]; 

The seven segment display will be indicated by lower case sw, dp, and an. The signals will be represented as a bus ranging from 0:max

[get_ports { seg[0] }];
[get_ports { seg[1] }];
[get_ports { seg[2] }];
[get_ports { seg[3] }];
[get_ports { seg[4] }];
[get_ports { seg[5] }];
[get_ports { seg[6] }];

[get_ports { an[0] }];
[get_ports { an[1] }];
[get_ports { an[2] }];
[get_ports { an[3] }];

[get_ports { dp }];

The Solomon Systech SSD1306 display controller SPI interface signals will be defined as follows.

# OLED Display
[get_ports { oled_dc }];
[get_ports { oled_res }]; 
[get_ports { oled_sclk }];
[get_ports { oled_sdin }];
[get_ports { oled_vbat }];
[get_ports { oled_vdd }]; 

The VGA interface signals will be defined as follows.

[get_ports { vga_r[0] }];
[get_ports { vga_r[1] }];
[get_ports { vga_r[2] }];
[get_ports { vga_r[3] }];

[get_ports { vga_g[0] }];
[get_ports { vga_g[1] }];
[get_ports { vga_g[2] }];
[get_ports { vga_g[3] }];

[get_ports { vga_b[0] }];
[get_ports { vga_b[1] }];
[get_ports { vga_b[2] }];
[get_ports { vga_b[3] }];

[get_ports { vga_hs }];
[get_ports { vga_vs }];

The HDMI in interface signals will be defined as follows.

 [get_ports { hdmi_rx_cec }]; 
 [get_ports { hdmi_rx_clk_n }];
 [get_ports { hdmi_rx_clk_p }];
 [get_ports { hdmi_rx_hpa }]; 
 [get_ports { hdmi_rx_scl }]; 
 [get_ports { hdmi_rx_sda }]; 
 [get_ports { hdmi_rx_txen }]; 
 [get_ports { hdmi_rx_n[0] }]; 
 [get_ports { hdmi_rx_p[0] }]; 
 [get_ports { hdmi_rx_n[1] }]; 
 [get_ports { hdmi_rx_p[1] }]; 
 [get_ports { hdmi_rx_n[2] }]; 
 [get_ports { hdmi_rx_p[2] }]; 

The HDMI out interface signals will be defined as follows.

[get_ports { hdmi_tx_cec }]; 
[get_ports { hdmi_tx_clk_n }];
[get_ports { hdmi_tx_clk_p }];
[get_ports { hdmi_tx_hpd }]; 
[get_ports { hdmi_tx_rscl }]; 
[get_ports { hdmi_tx_rsda }]; 
[get_ports { hdmi_tx_n[0] }]; 
[get_ports { hdmi_tx_p[0] }]; 
[get_ports { hdmi_tx_n[1] }]; 
[get_ports { hdmi_tx_p[1] }]; 
[get_ports { hdmi_tx_n[2] }]; 
[get_ports { hdmi_tx_p[2] }]; 

The Display Port interface signals will be defined as follows.

# Display Port
[get_ports { dp_tx_aux_n }];
[get_ports { dp_tx_aux_n }];
[get_ports { dp_tx_aux_p }];
[get_ports { dp_tx_aux_p }];
[get_ports { dp_tx_hpd }];