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wiki:xdcformat [2015/06/24 20:46] – Sam Lowewiki:xdcformat [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 ===== Memory ===== ===== Memory =====
  
-==== DDR3 ====+==== DDR ====
  
-The signals for the DDR3 Memory will be defined as follows. +DDR memory signals should not be included in the master XDC as the MIG IP will handle all of the signals. The user should receive a .prj and a .ucf file to navigate the MIG wizard with ease.
- +
-<code> +
- +
-# DDR3 +
-[get_ports { ddr3_addr[0] }];  +
-[get_ports { ddr3_addr[1] }];  +
-[get_ports { ddr3_addr[2] }];  +
-[get_ports { ddr3_addr[3] }];  +
-[get_ports { ddr3_addr[4] }];  +
-[get_ports { ddr3_addr[5] }];  +
-[get_ports { ddr3_addr[6] }];  +
-[get_ports { ddr3_addr[7] }];  +
-[get_ports { ddr3_addr[8] }];  +
-[get_ports { ddr3_addr[9] }];  +
-[get_ports { ddr3_addr[10] }]; +
-[get_ports { ddr3_addr[11] }]; +
-[get_ports { ddr3_addr[12] }]; +
-[get_ports { ddr3_addr[13] }]; +
-[get_ports { ddr3_addr[14] }]; +
-[get_ports { ddr3_ba[0] }];  +
-[get_ports { ddr3_ba[1] }];  +
-[get_ports { ddr3_ba[2] }];  +
-[get_ports { ddr3_cas }];  +
-[get_ports { ddr3_cke[0] }];  +
-[get_ports { ddr3_clk_n[0] }]; +
-[get_ports { ddr3_clk_p[0] }]; +
-[get_ports { ddr3_dm[0] }];  +
-[get_ports { ddr3_dm[1] }];  +
-[get_ports { ddr3_dq[0] }];  +
-[get_ports { ddr3_dq[1] }];  +
-[get_ports { ddr3_dq[2] }];  +
-[get_ports { ddr3_dq[3] }];  +
-[get_ports { ddr3_dq[4] }];  +
-[get_ports { ddr3_dq[5] }];  +
-[get_ports { ddr3_dq[6] }];  +
-[get_ports { ddr3_dq[7] }];  +
-[get_ports { ddr3_dq[8] }];  +
-[get_ports { ddr3_dq[9] }];  +
-[get_ports { ddr3_dq[10] }]; +
-[get_ports { ddr3_dq[11] }]; +
-[get_ports { ddr3_dq[12] }]; +
-[get_ports { ddr3_dq[13] }]; +
-[get_ports { ddr3_dq[14] }]; +
-[get_ports { ddr3_dq[15] }]; +
-[get_ports { ddr3_dqs_n[0] }]; +
-[get_ports { ddr3_dqs_p[0] }]; +
-[get_ports { ddr3_dqs_n[1] }]; +
-[get_ports { ddr3_dqs_p[1] }]; +
-[get_ports { ddr3_odt }];  +
-[get_ports { ddr3_ras }];  +
-[get_ports { ddr3_reset }]; +
-[get_ports { ddr3_we }];  +
- +
-</code>+
  
 ==== Cellular RAM ==== ==== Cellular RAM ====