Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
wiki:xdcformat [2015/06/24 20:24] – Sam Lowewiki:xdcformat [2022/10/04 11:38] (current) – external edit 127.0.0.1
Line 445: Line 445:
 ===== Memory ===== ===== Memory =====
  
-==== DDR3 ====+==== DDR ====
  
-The signals for the DDR3 Memory will be defined as follows.+DDR memory signals should not be included in the master XDC as the MIG IP will handle all of the signals. The user should receive a .prj and a .ucf file to navigate the MIG wizard with ease.
  
-[get_ports { ddr3_addr[0] }];  +==== Cellular RAM ====
-[get_ports { ddr3_addr[1] }];  +
-[get_ports { ddr3_addr[2] }];  +
-[get_ports { ddr3_addr[3] }];  +
-[get_ports { ddr3_addr[4] }];  +
-[get_ports { ddr3_addr[5] }];  +
-[get_ports { ddr3_addr[6] }];  +
-[get_ports { ddr3_addr[7] }];  +
-[get_ports { ddr3_addr[8] }];  +
-[get_ports { ddr3_addr[9] }];  +
-[get_ports { ddr3_addr[10] }]; +
-[get_ports { ddr3_addr[11] }]; +
-[get_ports { ddr3_addr[12] }]; +
-[get_ports { ddr3_addr[13] }]; +
-[get_ports { ddr3_addr[14] }]; +
-[get_ports { ddr3_ba[0] }];  +
-[get_ports { ddr3_ba[1] }];  +
-[get_ports { ddr3_ba[2] }];  +
-[get_ports { ddr3_cas }];  +
-[get_ports { ddr3_cke[0] }];  +
-[get_ports { ddr3_clk_n[0] }]; +
-[get_ports { ddr3_clk_p[0] }]; +
-[get_ports { ddr3_dm[0] }];  +
-[get_ports { ddr3_dm[1] }];  +
-[get_ports { ddr3_dq[0] }];  +
-[get_ports { ddr3_dq[1] }];  +
-[get_ports { ddr3_dq[2] }];  +
-[get_ports { ddr3_dq[3] }];  +
-[get_ports { ddr3_dq[4] }];  +
-[get_ports { ddr3_dq[5] }];  +
-[get_ports { ddr3_dq[6] }];  +
-[get_ports { ddr3_dq[7] }];  +
-[get_ports { ddr3_dq[8] }];  +
-[get_ports { ddr3_dq[9] }];  +
-[get_ports { ddr3_dq[10] }]; +
-[get_ports { ddr3_dq[11] }]; +
-[get_ports { ddr3_dq[12] }]; +
-[get_ports { ddr3_dq[13] }]; +
-[get_ports { ddr3_dq[14] }]; +
-[get_ports { ddr3_dq[15] }]; +
-[get_ports { ddr3_dqs_n[0] }]; +
-[get_ports { ddr3_dqs_p[0] }]; +
-[get_ports { ddr3_dqs_n[1] }]; +
-[get_ports { ddr3_dqs_p[1] }]; +
-[get_ports { ddr3_odt }];  +
-[get_ports { ddr3_ras }];  +
-[get_ports { ddr3_reset }]; +
-[get_ports { ddr3_we }]; +
  
 +The signals for the  Cellular RAM (Micron part number M45W8MW16) will be defined as follows.
  
 +<code>
  
 +# Cellular RAM
 +[get_ports { RamCLK }];
 +[get_ports { RamADVn }];
 +[get_ports { RamCEn }];
 +[get_ports { RamCRE }];
 +[get_ports { RamOEn }];
 +[get_ports { RamWEn }];
 +[get_ports { RamLBn }];
 +[get_ports { RamUBn }];
 +[get_ports { RamWait }];
  
 +
 +[get_ports { MemDB[0] }];
 +[get_ports { MemDB[1] }];
 +[get_ports { MemDB[2] }];
 +[get_ports { MemDB[3] }];
 +[get_ports { MemDB[4] }];
 +[get_ports { MemDB[5] }];
 +[get_ports { MemDB[6] }];
 +[get_ports { MemDB[7] }];
 +[get_ports { MemDB[8] }];
 +[get_ports { MemDB[9] }];
 +[get_ports { MemDB[10] }];
 +[get_ports { MemDB[11] }];
 +[get_ports { MemDB[12] }];
 +[get_ports { MemDB[13] }];
 +[get_ports { MemDB[14] }];
 +[get_ports { MemDB[15] }];
 +[get_ports { MemAdr[0] }];
 +[get_ports { MemAdr[1] }];
 +[get_ports { MemAdr[2] }];
 +[get_ports { MemAdr[3] }];
 +[get_ports { MemAdr[4] }];
 +[get_ports { MemAdr[5] }];
 +[get_ports { MemAdr[6] }];
 +[get_ports { MemAdr[7] }];
 +[get_ports { MemAdr[8] }];
 +[get_ports { MemAdr[9] }];
 +[get_ports { MemAdr[10] }];
 +[get_ports { MemAdr[11] }];
 +[get_ports { MemAdr[12] }];
 +[get_ports { MemAdr[13] }];
 +[get_ports { MemAdr[14] }];
 +[get_ports { MemAdr[15] }];
 +[get_ports { MemAdr[16] }];
 +[get_ports { MemAdr[17] }];
 +[get_ports { MemAdr[18] }];
 +[get_ports { MemAdr[19] }];
 +[get_ports { MemAdr[20] }];
 +[get_ports { MemAdr[21] }];
 +[get_ports { MemAdr[22] }];
 +
 +</code>
 +
 +==== SD Card ====
 +
 +<code>
 +
 +# SD card
 +[get_ports { sd_cclk }];
 +[get_ports { sd_cd }];
 +[get_ports { sd_cmd }]; 
 +[get_ports { sd_d[0] }];
 +[get_ports { sd_d[1] }];
 +[get_ports { sd_d[2] }];
 +[get_ports { sd_d[3] }];
 +[get_ports { sd_reset }];
 +[get_ports { sda }];
 +
 +</code>