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wiki:xdcformat [2015/06/24 20:17] – [Ethernet PHY] Sam Lowewiki:xdcformat [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 ===== Other Connections ===== ===== Other Connections =====
  
-==== Ethernet PHY ====+==== Ethernet ====
  
-The signals for the Analog Devices ADAU1761 SigmaDSP audio codec used on the Nexys Video will be defined as follows.+The signals for the Ethernet Port will be defined as follows.
  
 <code> <code>
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 </code> </code>
 +
 +==== FMC ====
 +
 +The signals for the FMC Port will be defined as follows.
 +
 +<code>
 +
 +# FMC
 +[get_ports { fmc_clk0_m2c_n }];
 +[get_ports { fmc_clk0_m2c_p }];
 +[get_ports { fmc_clk1_m2c_n }];
 +[get_ports { fmc_clk1_m2c_p }];
 +[get_ports { fmc_la00_cc_n }]; 
 +[get_ports { fmc_la00_cc_p }]; 
 +[get_ports { fmc_la01_cc_n }]; 
 +[get_ports { fmc_la01_cc_p }]; 
 +[get_ports { fmc_la_n[02] }]; 
 +[get_ports { fmc_la_p[02] }]; 
 +[get_ports { fmc_la_n[03] }]; 
 +[get_ports { fmc_la_p[03] }]; 
 +[get_ports { fmc_la_n[04] }]; 
 +[get_ports { fmc_la_p[04] }]; 
 +[get_ports { fmc_la_n[05] }]; 
 +[get_ports { fmc_la_p[05] }]; 
 +[get_ports { fmc_la_n[06] }]; 
 +[get_ports { fmc_la_p[06] }]; 
 +[get_ports { fmc_la_n[07] }]; 
 +[get_ports { fmc_la_p[07] }]; 
 +[get_ports { fmc_la_n[08] }]; 
 +[get_ports { fmc_la_p[08] }]; 
 +[get_ports { fmc_la_n[09] }]; 
 +[get_ports { fmc_la_p[09] }]; 
 +[get_ports { fmc_la_n[10] }]; 
 +[get_ports { fmc_la_p[10] }]; 
 +[get_ports { fmc_la_n[11] }]; 
 +[get_ports { fmc_la_p[11] }]; 
 +[get_ports { fmc_la_n[12] }]; 
 +[get_ports { fmc_la_p[12] }]; 
 +[get_ports { fmc_la_n[13] }]; 
 +[get_ports { fmc_la_p[13] }]; 
 +[get_ports { fmc_la_n[14] }]; 
 +[get_ports { fmc_la_p[14] }]; 
 +[get_ports { fmc_la_n[15] }]; 
 +[get_ports { fmc_la_p[15] }]; 
 +[get_ports { fmc_la_n[16] }]; 
 +[get_ports { fmc_la_p[16] }]; 
 +[get_ports { fmc_la17_cc_n }];
 +[get_ports { fmc_la17_cc_p }]; 
 +[get_ports { fmc_la18_cc_n }]; 
 +[get_ports { fmc_la18_cc_p }]; 
 +[get_ports { fmc_la_n[19] }]; 
 +[get_ports { fmc_la_p[19] }]; 
 +[get_ports { fmc_la_n[20] }]; 
 +[get_ports { fmc_la_p[20] }]; 
 +[get_ports { fmc_la_n[21] }]; 
 +[get_ports { fmc_la_p[21] }]; 
 +[get_ports { fmc_la_n[22] }]; 
 +[get_ports { fmc_la_p[22] }]; 
 +[get_ports { fmc_la_n[23] }]; 
 +[get_ports { fmc_la_p[23] }]; 
 +[get_ports { fmc_la_n[24] }]; 
 +[get_ports { fmc_la_p[24] }]; 
 +[get_ports { fmc_la_n[25] }]; 
 +[get_ports { fmc_la_p[25] }]; 
 +[get_ports { fmc_la_n[26] }]; 
 +[get_ports { fmc_la_p[26] }]; 
 +[get_ports { fmc_la_n[27] }]; 
 +[get_ports { fmc_la_p[27] }]; 
 +[get_ports { fmc_la_n[28] }]; 
 +[get_ports { fmc_la_p[28] }]; 
 +[get_ports { fmc_la_n[29] }]; 
 +[get_ports { fmc_la_p[29] }]; 
 +[get_ports { fmc_la_n[30] }]; 
 +[get_ports { fmc_la_p[30] }]; 
 +[get_ports { fmc_la_n[31] }]; 
 +[get_ports { fmc_la_p[31] }]; 
 +[get_ports { fmc_la_n[32] }]; 
 +[get_ports { fmc_la_p[32] }]; 
 +[get_ports { fmc_la_n[33] }]; 
 +[get_ports { fmc_la_p[33] }]; 
 +
 +[get_ports { vrefa_m2c }]; 
 +[get_ports { vrefa_m2c }]; 
 +[get_ports { vrefa_m2c }]; 
 +[get_ports { vrefa_m2c }]; 
 +
 +[get_ports { prsnt_m2c }]; 
 +
 +</code>
 +
 +===== Memory =====
 +
 +==== DDR ====
 +
 +DDR memory signals should not be included in the master XDC as the MIG IP will handle all of the signals. The user should receive a .prj and a .ucf file to navigate the MIG wizard with ease.
 +
 +==== Cellular RAM ====
 +
 +The signals for the  Cellular RAM (Micron part number M45W8MW16) will be defined as follows.
 +
 +<code>
 +
 +# Cellular RAM
 +[get_ports { RamCLK }];
 +[get_ports { RamADVn }];
 +[get_ports { RamCEn }];
 +[get_ports { RamCRE }];
 +[get_ports { RamOEn }];
 +[get_ports { RamWEn }];
 +[get_ports { RamLBn }];
 +[get_ports { RamUBn }];
 +[get_ports { RamWait }];
 +
 +
 +[get_ports { MemDB[0] }];
 +[get_ports { MemDB[1] }];
 +[get_ports { MemDB[2] }];
 +[get_ports { MemDB[3] }];
 +[get_ports { MemDB[4] }];
 +[get_ports { MemDB[5] }];
 +[get_ports { MemDB[6] }];
 +[get_ports { MemDB[7] }];
 +[get_ports { MemDB[8] }];
 +[get_ports { MemDB[9] }];
 +[get_ports { MemDB[10] }];
 +[get_ports { MemDB[11] }];
 +[get_ports { MemDB[12] }];
 +[get_ports { MemDB[13] }];
 +[get_ports { MemDB[14] }];
 +[get_ports { MemDB[15] }];
 +[get_ports { MemAdr[0] }];
 +[get_ports { MemAdr[1] }];
 +[get_ports { MemAdr[2] }];
 +[get_ports { MemAdr[3] }];
 +[get_ports { MemAdr[4] }];
 +[get_ports { MemAdr[5] }];
 +[get_ports { MemAdr[6] }];
 +[get_ports { MemAdr[7] }];
 +[get_ports { MemAdr[8] }];
 +[get_ports { MemAdr[9] }];
 +[get_ports { MemAdr[10] }];
 +[get_ports { MemAdr[11] }];
 +[get_ports { MemAdr[12] }];
 +[get_ports { MemAdr[13] }];
 +[get_ports { MemAdr[14] }];
 +[get_ports { MemAdr[15] }];
 +[get_ports { MemAdr[16] }];
 +[get_ports { MemAdr[17] }];
 +[get_ports { MemAdr[18] }];
 +[get_ports { MemAdr[19] }];
 +[get_ports { MemAdr[20] }];
 +[get_ports { MemAdr[21] }];
 +[get_ports { MemAdr[22] }];
 +
 +</code>
 +
 +==== SD Card ====
 +
 +<code>
 +
 +# SD card
 +[get_ports { sd_cclk }];
 +[get_ports { sd_cd }];
 +[get_ports { sd_cmd }]; 
 +[get_ports { sd_d[0] }];
 +[get_ports { sd_d[1] }];
 +[get_ports { sd_d[2] }];
 +[get_ports { sd_d[3] }];
 +[get_ports { sd_reset }];
 +[get_ports { sda }];
 +
 +</code>
 +