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wiki:xdcformat [2015/06/24 00:38] – Sam Lowewiki:xdcformat [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 ====== XDC Formatting Info ====== ====== XDC Formatting Info ======
  
-This Guide is to standardize our format for XDCs. All Digilent XDCs should follow this format to help ease the transfer of projects between boards.+This Guide is to standardize our format for XDCs. All Digilent XDCs should follow this format to help ease the transfer of projects between boards. The standard format will also improve the look of our XDC code.
 ----- -----
 +
 +===== Line Format =====
 +
 +All the XDCs should use the one line format which can be generated through EAGLE. The basic format is below. The only thing that the below sections will show is how to properly fill the (signal name) section. The other portions need to come from the board schematic.
 +
 +<code>
 +
 +#set_property -dict { PACKAGE_PIN X   IOSTANDARD X } [get_ports { (signal name) }]; #(fpga port) Sch=(schematic name)
 +
 +</code>
  
 ===== GPIO ===== ===== GPIO =====
Line 12: Line 22:
 <code> <code>
  
 +# Switches
 [get_ports { sw[0] }]; [get_ports { sw[0] }];
 [get_ports { sw[1] }]; [get_ports { sw[1] }];
Line 29: Line 40:
 <code> <code>
  
 +# LEDs
 [get_ports { led[0] }]; [get_ports { led[0] }];
 [get_ports { led[1] }]; [get_ports { led[1] }];
Line 48: Line 60:
 <code> <code>
  
 +# Buttons
 [get_ports { btnc }]; [get_ports { btnc }];
 [get_ports { btnd }]; [get_ports { btnd }];
Line 62: Line 75:
 <code> <code>
  
 +# Buttons
 [get_ports { btn[0] }]; [get_ports { btn[0] }];
 [get_ports { btn[1] }]; [get_ports { btn[1] }];
Line 81: Line 95:
 ==== Pmod Headers ==== ==== Pmod Headers ====
  
-The pmod headers will be designated by Jx where x is the letter specifying which header is used. The ports should be numbered from 0 to 7. This will let the user use the name as a bus.+The pmod headers will be designated by jx where x is the letter specifying which header is used. The ports should be numbered from 0 to 7. This will let the user use the name as a bus.
  
 <code> <code>
  
 +# Pmod header JX
 [get_ports { jx[0] }]; [get_ports { jx[0] }];
 [get_ports { jx[1] }]; [get_ports { jx[1] }];
Line 95: Line 110:
  
 </code> </code>
 +
 +==== XADC Pmod Headers ====
 +
 +The XADC pmod headers will be designated by xa_n or xa_p and numbered from 0 - 3 to be used as a bus. 
 +
 +<code>
 +
 +# XADC Header 
 +[get_ports { xa_n[0] }];
 +[get_ports { xa_p[0] }];
 +[get_ports { xa_n[1] }];
 +[get_ports { xa_p[1] }];
 +[get_ports { xa_n[2] }];
 +[get_ports { xa_p[2] }];
 +[get_ports { xa_n[3] }];
 +[get_ports { xa_p[3] }];
 +
 +</code>
 +
 +==== UART Interface ====
 +
 +The two UART signals will be named as follows
 +
 +
 +<code>
 +
 +# UART
 +[get_ports { uart_rx_out }];
 +[get_ports { uart_tx_in }]; 
 +
 +</code>
 +
 +==== Seven Seg Display ====
 +
 +The seven segment display will be indicated by lower case sw, dp, and an. The signals will be represented as a bus ranging from 0:max
 +
 +
 +<code>
 +
 +# 7 segment display
 +[get_ports { seg[0] }];
 +[get_ports { seg[1] }];
 +[get_ports { seg[2] }];
 +[get_ports { seg[3] }];
 +[get_ports { seg[4] }];
 +[get_ports { seg[5] }];
 +[get_ports { seg[6] }];
 +
 +[get_ports { an[0] }];
 +[get_ports { an[1] }];
 +[get_ports { an[2] }];
 +[get_ports { an[3] }];
 +
 +[get_ports { dp }];
 +
 +
 +</code>
 +
 +==== OLED Display ====
 +
 +The Solomon Systech SSD1306 display controller SPI interface signals will be defined as follows.
 +
 +
 +<code>
 +
 +# OLED Display
 +[get_ports { oled_dc }];
 +[get_ports { oled_res }]; 
 +[get_ports { oled_sclk }];
 +[get_ports { oled_sdin }];
 +[get_ports { oled_vbat }];
 +[get_ports { oled_vdd }]; 
 +
 +</code>
 +
 +==== HID Port ====
 +
 +The PS2 HID host signals for a mouse and keyboard will be defined as follows.
 +
 +
 +<code>
 +
 +# HID port
 +[get_ports { ps2_clk }]; 
 +[get_ports { ps2_data }];
 +
 +</code>
 +
 +===== Video =====
 +
 +==== VGA ====
 +
 +The VGA interface signals will be defined as follows.
 +
 +
 +<code>
 +
 +# VGA Connector
 +[get_ports { vga_r[0] }];
 +[get_ports { vga_r[1] }];
 +[get_ports { vga_r[2] }];
 +[get_ports { vga_r[3] }];
 +
 +[get_ports { vga_g[0] }];
 +[get_ports { vga_g[1] }];
 +[get_ports { vga_g[2] }];
 +[get_ports { vga_g[3] }];
 +
 +[get_ports { vga_b[0] }];
 +[get_ports { vga_b[1] }];
 +[get_ports { vga_b[2] }];
 +[get_ports { vga_b[3] }];
 +
 +[get_ports { vga_hs }];
 +[get_ports { vga_vs }];
 +
 +
 +
 +</code>
 +
 +==== HDMI in ====
 +
 +The HDMI in interface signals will be defined as follows.
 +
 +
 +<code>
 +
 + # HDMI in
 + [get_ports { hdmi_rx_cec }]; 
 + [get_ports { hdmi_rx_clk_n }];
 + [get_ports { hdmi_rx_clk_p }];
 + [get_ports { hdmi_rx_hpa }]; 
 + [get_ports { hdmi_rx_scl }]; 
 + [get_ports { hdmi_rx_sda }]; 
 + [get_ports { hdmi_rx_txen }]; 
 + [get_ports { hdmi_rx_n[0] }]; 
 + [get_ports { hdmi_rx_p[0] }]; 
 + [get_ports { hdmi_rx_n[1] }]; 
 + [get_ports { hdmi_rx_p[1] }]; 
 + [get_ports { hdmi_rx_n[2] }]; 
 + [get_ports { hdmi_rx_p[2] }]; 
 +
 +
 +</code>
 +
 +==== HDMI out ====
 +
 +The HDMI out interface signals will be defined as follows.
 +
 +
 +<code>
 +
 +# HDMI out
 +[get_ports { hdmi_tx_cec }]; 
 +[get_ports { hdmi_tx_clk_n }];
 +[get_ports { hdmi_tx_clk_p }];
 +[get_ports { hdmi_tx_hpd }]; 
 +[get_ports { hdmi_tx_rscl }]; 
 +[get_ports { hdmi_tx_rsda }]; 
 +[get_ports { hdmi_tx_n[0] }]; 
 +[get_ports { hdmi_tx_p[0] }]; 
 +[get_ports { hdmi_tx_n[1] }]; 
 +[get_ports { hdmi_tx_p[1] }]; 
 +[get_ports { hdmi_tx_n[2] }]; 
 +[get_ports { hdmi_tx_p[2] }]; 
 +
 +</code>
 +
 +==== Display Port ====
 +
 +The Display Port interface signals will be defined as follows.
 +
 +
 +<code>
 +
 +# Display Port
 +[get_ports { dp_tx_aux_n }];
 +[get_ports { dp_tx_aux_n }];
 +[get_ports { dp_tx_aux_p }];
 +[get_ports { dp_tx_aux_p }];
 +[get_ports { dp_tx_hpd }]; 
 +
 +
 +</code>
 +
 +===== Audio =====
 +
 +==== PWM Audio Amplifier ====
 +
 +The signals for the PWM audio out will be defined as follows.
 +
 +<code>
 +
 +# PWM Audio Amplifier
 +[get_ports { aud_pwm }];
 +[get_ports { aud_sd }]; 
 +
 +</code>
 +
 +==== Audio Codec ====
 +
 +The signals for the Analog Devices ADAU1761 SigmaDSP audio codec used on the Nexys Video will be defined as follows.
 +
 +<code>
 +
 +# Audio Codec
 +[get_ports { ac_adc_sdata }];
 +[get_ports { ac_bclk }]; 
 +[get_ports { ac_dac_sdata }];
 +[get_ports { ac_lrclk }]; 
 +[get_ports { ac_mclk }]; 
 +
 +
 +</code>
 +
 +===== Other Connections =====
 +
 +==== Ethernet ====
 +
 +The signals for the Ethernet Port will be defined as follows.
 +
 +<code>
 +
 +# Ethernet
 +[get_ports { eth_int_b }]; 
 +[get_ports { eth_mdc }]; 
 +[get_ports { eth_mdio }]; 
 +[get_ports { eth_pme_b }]; 
 +[get_ports { eth_rst_b }]; 
 +[get_ports { eth_rxck }]; 
 +[get_ports { eth_rxctl }]; 
 +[get_ports { eth_rxd[0] }];
 +[get_ports { eth_rxd[1] }];
 +[get_ports { eth_rxd[2] }];
 +[get_ports { eth_rxd[3] }];
 +[get_ports { eth_txck }]; 
 +[get_ports { eth_txctl }]; 
 +[get_ports { eth_txd[0] }];
 +[get_ports { eth_txd[1] }];
 +[get_ports { eth_txd[2] }];
 +[get_ports { eth_txd[3] }];\
 +
 +</code>
 +
 +==== FMC ====
 +
 +The signals for the FMC Port will be defined as follows.
 +
 +<code>
 +
 +# FMC
 +[get_ports { fmc_clk0_m2c_n }];
 +[get_ports { fmc_clk0_m2c_p }];
 +[get_ports { fmc_clk1_m2c_n }];
 +[get_ports { fmc_clk1_m2c_p }];
 +[get_ports { fmc_la00_cc_n }]; 
 +[get_ports { fmc_la00_cc_p }]; 
 +[get_ports { fmc_la01_cc_n }]; 
 +[get_ports { fmc_la01_cc_p }]; 
 +[get_ports { fmc_la_n[02] }]; 
 +[get_ports { fmc_la_p[02] }]; 
 +[get_ports { fmc_la_n[03] }]; 
 +[get_ports { fmc_la_p[03] }]; 
 +[get_ports { fmc_la_n[04] }]; 
 +[get_ports { fmc_la_p[04] }]; 
 +[get_ports { fmc_la_n[05] }]; 
 +[get_ports { fmc_la_p[05] }]; 
 +[get_ports { fmc_la_n[06] }]; 
 +[get_ports { fmc_la_p[06] }]; 
 +[get_ports { fmc_la_n[07] }]; 
 +[get_ports { fmc_la_p[07] }]; 
 +[get_ports { fmc_la_n[08] }]; 
 +[get_ports { fmc_la_p[08] }]; 
 +[get_ports { fmc_la_n[09] }]; 
 +[get_ports { fmc_la_p[09] }]; 
 +[get_ports { fmc_la_n[10] }]; 
 +[get_ports { fmc_la_p[10] }]; 
 +[get_ports { fmc_la_n[11] }]; 
 +[get_ports { fmc_la_p[11] }]; 
 +[get_ports { fmc_la_n[12] }]; 
 +[get_ports { fmc_la_p[12] }]; 
 +[get_ports { fmc_la_n[13] }]; 
 +[get_ports { fmc_la_p[13] }]; 
 +[get_ports { fmc_la_n[14] }]; 
 +[get_ports { fmc_la_p[14] }]; 
 +[get_ports { fmc_la_n[15] }]; 
 +[get_ports { fmc_la_p[15] }]; 
 +[get_ports { fmc_la_n[16] }]; 
 +[get_ports { fmc_la_p[16] }]; 
 +[get_ports { fmc_la17_cc_n }];
 +[get_ports { fmc_la17_cc_p }]; 
 +[get_ports { fmc_la18_cc_n }]; 
 +[get_ports { fmc_la18_cc_p }]; 
 +[get_ports { fmc_la_n[19] }]; 
 +[get_ports { fmc_la_p[19] }]; 
 +[get_ports { fmc_la_n[20] }]; 
 +[get_ports { fmc_la_p[20] }]; 
 +[get_ports { fmc_la_n[21] }]; 
 +[get_ports { fmc_la_p[21] }]; 
 +[get_ports { fmc_la_n[22] }]; 
 +[get_ports { fmc_la_p[22] }]; 
 +[get_ports { fmc_la_n[23] }]; 
 +[get_ports { fmc_la_p[23] }]; 
 +[get_ports { fmc_la_n[24] }]; 
 +[get_ports { fmc_la_p[24] }]; 
 +[get_ports { fmc_la_n[25] }]; 
 +[get_ports { fmc_la_p[25] }]; 
 +[get_ports { fmc_la_n[26] }]; 
 +[get_ports { fmc_la_p[26] }]; 
 +[get_ports { fmc_la_n[27] }]; 
 +[get_ports { fmc_la_p[27] }]; 
 +[get_ports { fmc_la_n[28] }]; 
 +[get_ports { fmc_la_p[28] }]; 
 +[get_ports { fmc_la_n[29] }]; 
 +[get_ports { fmc_la_p[29] }]; 
 +[get_ports { fmc_la_n[30] }]; 
 +[get_ports { fmc_la_p[30] }]; 
 +[get_ports { fmc_la_n[31] }]; 
 +[get_ports { fmc_la_p[31] }]; 
 +[get_ports { fmc_la_n[32] }]; 
 +[get_ports { fmc_la_p[32] }]; 
 +[get_ports { fmc_la_n[33] }]; 
 +[get_ports { fmc_la_p[33] }]; 
 +
 +[get_ports { vrefa_m2c }]; 
 +[get_ports { vrefa_m2c }]; 
 +[get_ports { vrefa_m2c }]; 
 +[get_ports { vrefa_m2c }]; 
 +
 +[get_ports { prsnt_m2c }]; 
 +
 +</code>
 +
 +===== Memory =====
 +
 +==== DDR ====
 +
 +DDR memory signals should not be included in the master XDC as the MIG IP will handle all of the signals. The user should receive a .prj and a .ucf file to navigate the MIG wizard with ease.
 +
 +==== Cellular RAM ====
 +
 +The signals for the  Cellular RAM (Micron part number M45W8MW16) will be defined as follows.
 +
 +<code>
 +
 +# Cellular RAM
 +[get_ports { RamCLK }];
 +[get_ports { RamADVn }];
 +[get_ports { RamCEn }];
 +[get_ports { RamCRE }];
 +[get_ports { RamOEn }];
 +[get_ports { RamWEn }];
 +[get_ports { RamLBn }];
 +[get_ports { RamUBn }];
 +[get_ports { RamWait }];
 +
 +
 +[get_ports { MemDB[0] }];
 +[get_ports { MemDB[1] }];
 +[get_ports { MemDB[2] }];
 +[get_ports { MemDB[3] }];
 +[get_ports { MemDB[4] }];
 +[get_ports { MemDB[5] }];
 +[get_ports { MemDB[6] }];
 +[get_ports { MemDB[7] }];
 +[get_ports { MemDB[8] }];
 +[get_ports { MemDB[9] }];
 +[get_ports { MemDB[10] }];
 +[get_ports { MemDB[11] }];
 +[get_ports { MemDB[12] }];
 +[get_ports { MemDB[13] }];
 +[get_ports { MemDB[14] }];
 +[get_ports { MemDB[15] }];
 +[get_ports { MemAdr[0] }];
 +[get_ports { MemAdr[1] }];
 +[get_ports { MemAdr[2] }];
 +[get_ports { MemAdr[3] }];
 +[get_ports { MemAdr[4] }];
 +[get_ports { MemAdr[5] }];
 +[get_ports { MemAdr[6] }];
 +[get_ports { MemAdr[7] }];
 +[get_ports { MemAdr[8] }];
 +[get_ports { MemAdr[9] }];
 +[get_ports { MemAdr[10] }];
 +[get_ports { MemAdr[11] }];
 +[get_ports { MemAdr[12] }];
 +[get_ports { MemAdr[13] }];
 +[get_ports { MemAdr[14] }];
 +[get_ports { MemAdr[15] }];
 +[get_ports { MemAdr[16] }];
 +[get_ports { MemAdr[17] }];
 +[get_ports { MemAdr[18] }];
 +[get_ports { MemAdr[19] }];
 +[get_ports { MemAdr[20] }];
 +[get_ports { MemAdr[21] }];
 +[get_ports { MemAdr[22] }];
 +
 +</code>
 +
 +==== SD Card ====
 +
 +<code>
 +
 +# SD card
 +[get_ports { sd_cclk }];
 +[get_ports { sd_cd }];
 +[get_ports { sd_cmd }]; 
 +[get_ports { sd_d[0] }];
 +[get_ports { sd_d[1] }];
 +[get_ports { sd_d[2] }];
 +[get_ports { sd_d[3] }];
 +[get_ports { sd_reset }];
 +[get_ports { sda }];
 +
 +</code>
 +