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waveforms_-_rom_logic [2016/11/28 11:25] – [4. Example: Three input, synchronous AND gate.] Mircea Dabacanwaveforms_-_rom_logic [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 //{{anchor:figure_3:Figure 3 ROM Logic implementing a Mealy State Machine.}}// //{{anchor:figure_3:Figure 3 ROM Logic implementing a Mealy State Machine.}}//
  
-===== 3. ROM logic User Interface in WaveForms 2015 =====+===== 3. ROM logic User Interface in WaveForms =====
  
 In the Pattern Generator, click the green “plus” sign and select ROM logic, as shown below. In the Pattern Generator, click the green “plus” sign and select ROM logic, as shown below.
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 In Figure 5, the ROM logic object is named AND3 (optional). DIO0…DIO2 are selected as inputs, DIO3 as output. The signal names are changed to i0…i2, respectively o3 (optional). The synchronizing frequency is set to 5MHz, meaning the output signal will be synchronized to a 5MHz clock with 0° phase, relative to the moment of running the Pattern Generator; this way, the output signal is synchronized to other signals generated by the Pattern generator.  In Figure 5, the ROM logic object is named AND3 (optional). DIO0…DIO2 are selected as inputs, DIO3 as output. The signal names are changed to i0…i2, respectively o3 (optional). The synchronizing frequency is set to 5MHz, meaning the output signal will be synchronized to a 5MHz clock with 0° phase, relative to the moment of running the Pattern Generator; this way, the output signal is synchronized to other signals generated by the Pattern generator. 
  
-In the Truth Table tab, the first line describes the default case, with the output signal value of 0. With three X-es in the input pane, this line is equivalent to 23=8 expanded lines. However, the second line overrides one line out of the eight, forcing the output signal to 1 when all inputs are 1.+In the Truth Table tab, the first line describes the default case, with the output signal value of 0. With three X-es in the input pane, this line is equivalent to 2<sup>3</sup>=8 expanded lines. However, the second line overrides one line out of the eight, forcing the output signal to 1 when all inputs are 1.
 The equivalent VHDL code is: The equivalent VHDL code is:
        
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 ===== 5. Example: Binary counter with Count Enable input. ===== ===== 5. Example: Binary counter with Count Enable input. =====
  
-In the figure below, DIO8 is renamed CE and is used as Count Enable. DIO7…DIO0 are renamed c7…c0 and are the state/output bits of the 8-bit binary counter. Notice how X-es, signal names, and negated signal names are used in the Truth Table. The clock for the counter is 100kHz. The Truth Table was written in Excel (colored background area in sheet CounterWithCe8Bit of RomLogicTruthTables.xls) and copied in the appropriate tab.+In the figure below, DIO8 is renamed CE and is used as Count Enable. DIO7…DIO0 are renamed c7…c0 and are the state/output bits of the 8-bit binary counter. Notice how X-es, signal names, and negated signal names are used in the Truth Table. The clock for the counter is 100kHz. The Truth Table was written in Excel (colored background area in sheet CounterWithCe8Bit of {{:waveformsromlogic:RomLogicTruthTables.xlsx|RomLogicTruthTables.xlsx}}) and copied in the appropriate tab.
  
-Line 1 in the Truth Table (equivalent to 28=256 expanded lines) means: when LSB c0=’0’: all bits c7…c1 keep value; c0 changes to ‘1’ only if CE=’1’. All other lines cover the cases when c0=’1’.+Line 1 in the Truth Table (equivalent to 2<sup>8</sup>=256 expanded lines) means: when LSB c0=’0’: all bits c7…c1 keep value; c0 changes to ‘1’ only if CE=’1’. All other lines cover the cases when c0=’1’.
  
-Line 2 (equivalent to 27=128 expanded lines): means when c1=’0’ and c0=’1’: both will swap if CE=’1’ or keep their value if CE=’0’; all other bits keep their value.+Line 2 (equivalent to 2<sup>7</sup>=128 expanded lines): means when c1=’0’ and c0=’1’: both will swap if CE=’1’ or keep their value if CE=’0’; all other bits keep their value.
  
-All nine lines are equivalent to 29=512 expanded lines and define all possible cases (8 bit+1 Count Enable).+All nine lines are equivalent to 2<sup>9</sup>=512 expanded lines and define all possible cases (8 bit+1 Count Enable).
  
 To verify the behavior, add a clock signal on DIO8 (Frequency=1kHz, Duty Factor=80%). As defined above, DIO8 is Count Enable for the binary counter.  To verify the behavior, add a clock signal on DIO8 (Frequency=1kHz, Duty Factor=80%). As defined above, DIO8 is Count Enable for the binary counter. 
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 //{{anchor:figure_10:Figure 10.Pattern Generator prepared for PWM with static input.}}// //{{anchor:figure_10:Figure 10.Pattern Generator prepared for PWM with static input.}}//
  
-A 5-bit counter is implemented in a ROM logic object, as below, on DIO9…DIO5, renamed c4…c0. The Truth Table was written in Excel (sheet PWM in RomLogicTrouthTables.xls) and copied in the Truth Table tab. The clock frequency is set to 1MHz.+A 5-bit counter is implemented in a ROM logic object, as below, on DIO9…DIO5, renamed c4…c0. The Truth Table was written in Excel (sheet PWM in {{:waveformsromlogic:RomLogicTruthTables.xlsx|RomLogicTruthTables.xlsx}}) and copied in the Truth Table tab. The clock frequency is set to 1MHz.
  
 {{:waveformsromlogic:RL_11_5BitCounterRomLogic.png|Figure 11. 5 bit counter ROM logic.}} {{:waveformsromlogic:RL_11_5BitCounterRomLogic.png|Figure 11. 5 bit counter ROM logic.}}
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 //{{anchor:figure_11:Figure 11. 5 bit counter ROM logic.}}// //{{anchor:figure_11:Figure 11. 5 bit counter ROM logic.}}//
  
-A second ROM logic (sheet PWM in RomLogicTrouthTables.xls) compares DIO9…DIO5 = c4…c0 = “5BitCounter” with DIO4…DIO0 = s4…s0 = ”Sample”. DIO10 = CY = ”CarryOut” is High when “Sample” is higher. Notice again how higher order bits (later lines in the Truth Table) override the lower order bits (earlier lines in the Truth Table).+A second ROM logic (sheet PWM in {{:waveformsromlogic:RomLogicTruthTables.xlsx|RomLogicTruthTables.xlsx}}) compares DIO9…DIO5 = c4…c0 = “5BitCounter” with DIO4…DIO0 = s4…s0 = ”Sample”. DIO10 = CY = ”CarryOut” is High when “Sample” is higher. Notice again how higher order bits (later lines in the Truth Table) override the lower order bits (earlier lines in the Truth Table).
  
 {{:waveformsromlogic:RL_12_5By5BitComparatorRomLogic.png|Figure 12. 5-by-5 bit Comparator ROM logic.}} {{:waveformsromlogic:RL_12_5By5BitComparatorRomLogic.png|Figure 12. 5-by-5 bit Comparator ROM logic.}}
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 //{{anchor:figure_14:Figure 14. Static PWM Scope capture.}}// //{{anchor:figure_14:Figure 14. Static PWM Scope capture.}}//
  
-Variable n-bit sample can be used as a modulator signal. For the second experiment, set a custom 5-bit Bus 1 in the Pattern Generator, to drive a sinus signal with 100 samples per period. Generate a .csv file, with 100 values of form (sheet SinusSamples in RomLogicTrouthTables.xls):+Variable n-bit sample can be used as a modulator signal. For the second experiment, set a custom 5-bit Bus 1 in the Pattern Generator, to drive a sinus signal with 100 samples per period. Generate a .csv file, with 100 values of form (sheet SinusSamples in {{:waveformsromlogic:RomLogicTruthTables.xlsx|RomLogicTruthTables.xlsx}}):
  
 $$sample_i=16+int(15*sin((2∙π∙i)/100))∈[1…31]$$ $$sample_i=16+int(15*sin((2∙π∙i)/100))∈[1…31]$$
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 ===== 7. Example: PDM modulator. ===== ===== 7. Example: PDM modulator. =====
  
-In the figure below, an n-bit accumulator is used to add the sample value over and over. The Carry Out bit is the Pulse Density Modulated (PDM) signal. The accumulator is refreshed with fcnt frequency, while samples succeed with fsample rate. Same frequencies and names are used as for PWM, for comparison.+In the figure below, an n-bit accumulator is used to add the sample value over and over. The Carry Out bit is the Pulse Density Modulated (PDM) signal. The accumulator is refreshed with f<sub>cnt</sub> frequency, while samples succeed with f<sub>sample</sub> rate. Same frequencies and names are used as for PWM, for comparison.
  
 {{:waveformsromlogic:RL_17_PdmModulatorBlockDiagram.png|Figure 17. PDM modulator block diagram.}} {{:waveformsromlogic:RL_17_PdmModulatorBlockDiagram.png|Figure 17. PDM modulator block diagram.}}
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 //{{anchor:figure_18:Figure 18. Open a second pattern generator.}}// //{{anchor:figure_18:Figure 18. Open a second pattern generator.}}//
  
- A 5-bit PDM modulator is implemented in the PDM Accumulator ROM logic object, with DIO 9…DIO5 = a4…a0 as “Accumulator”, DIO4…DIO0 = s4…s0 as “Sample” and DIO10 as “CY” which is the PDM signal (copy colored background area in sheet PDM of RomLogicTrouthTables.xls and paste into the Truth Table).+ A 5-bit PDM modulator is implemented in the PDM Accumulator ROM logic object, with DIO 9…DIO5 = a4…a0 as “Accumulator”, DIO4…DIO0 = s4…s0 as “Sample” and DIO10 as “CY” which is the PDM signal (copy colored background area in sheet PDM of {{:waveformsromlogic:RomLogicTruthTables.xlsx|RomLogicTruthTables.xlsx}} and paste into the Truth Table).
  
 {{:waveformsromlogic:RL_19_OpenASecondPatternGenerator.png|Figure 19. Implementing a PDM in ROM logic.}} {{:waveformsromlogic:RL_19_OpenASecondPatternGenerator.png|Figure 19. Implementing a PDM in ROM logic.}}
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 $$(CY,a4…a0) <= (a4…a0) + (s4…s0)$$ $$(CY,a4…a0) <= (a4…a0) + (s4…s0)$$
  
-To compare with PWM, similar examples are used. The same external RC filter, the clock frequency of the modulator, the sinus sample LUT and sample frequency are all the same as in the corresponding PWM experiments. +To compare with PWM, similar examples are used. The same external RC filter, the clock frequency of the modulator, the sinus Sample Memory and sample frequency are all the same as in the corresponding PWM experiments. 
  
 In the static experiment, the same duty factor is generated, with a much higher frequency, resulting in a much smaller ripple of the analog signal.  In the static experiment, the same duty factor is generated, with a much higher frequency, resulting in a much smaller ripple of the analog signal. 
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 In the dynamic experiment, the same sinus custom Bus1 was used, as for the PWM. The average Duty Factor is again around 50%, the frequency is variable and the average frequency is much higher compared to PWM, for the same clock frequency. The ripple of the analog signal is also much smaller. In the dynamic experiment, the same sinus custom Bus1 was used, as for the PWM. The average Duty Factor is again around 50%, the frequency is variable and the average frequency is much higher compared to PWM, for the same clock frequency. The ripple of the analog signal is also much smaller.
  
-The lowest instantaneous frequency of the PDM signal happens when the sample value is either 1LSB or 2n-1LSB, and is the same as the constant frequency of the PWM signal. For all other values of the samples, the resulting instantaneous frequency is higher, up to half of the clock frequency, when the sample value is at half of the range.  +The lowest instantaneous frequency of the PDM signal happens when the sample value is either 1LSB or 2<sup>n</sup>-1LSB, and is the same as the constant frequency of the PWM signal. For all other values of the samples, the resulting instantaneous frequency is higher, up to half of the clock frequency, when the sample value is at half of the range.  
  
 Having both instances of the Pattern generator open, is very easy to run them alternatively for easy comparison on the scope instrument. Hitting Run on one instance automatically turns the other instance in Busy state. Having both instances of the Pattern generator open, is very easy to run them alternatively for easy comparison on the scope instrument. Hitting Run on one instance automatically turns the other instance in Busy state.