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vivado:ws_zynq [2016/01/06 22:26] – Andrew Holzervivado:ws_zynq [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 =====Overview===== =====Overview=====
-This workshops serves to introduce you to the system design flow for ZYNQ using Vivado. The workshop is split into six labs that explore tools and processes important to the design flow. +This workshops serves to introduce you to the system design flow for ZYNQ using  
 +Vivado. The workshop is split into six labs that explore tools and processes  
 +important to the design flow. The labs are as follows
    
-  * Lab1  +  * Lab1 teaches you the Vivado design flow to create an HDL design. You will learn to simulate, synthesize, implement and verify the design in hardware.  
-  * Lab2 +  * Lab2 has you create a project using the I/O planning tools after which you'll export the design to rtl. Using XDC timing constraints you'll perform a timing analysis of the design. 
-  * Lab3  +  * Using the IP Integrator you'll create an ARM Cortex-A9 processor based design in Lab3. You'll export the hardware design and develop an application in the SDK in order to verify the hardware. 
-  * Lab4 +  * Lab4 has you create a custom AXI4Lite peripheral and add it to a processor system in the IP Packager. 
-  * Lab5 +  * In Lab5 you'll learn to use powerful IP cores to debug the hardware, and use the SDK to perform software debugging. 
-  * Lab6 +  * You'll learn the design flow to creating an IP-XACT adapter using Vivado HLS in Lab6. The generated adapter is then used in a processor system design.
  
 After completing this workshop's series of labs, you should be able to: After completing this workshop's series of labs, you should be able to:
-  * +  * Use XDC files to communicate performance. 
 +  * Design an embedded system that targets the ARM processor of the ZYNQ chip. 
 +  * Create custom peripherals. 
 +  * Extend the hardware system with the Xilinx peripherals and/or custom peripherals.
  
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 ===Hardware=== ===Hardware===
   * **Digilent Zedboard or Zybo board**   * **Digilent Zedboard or Zybo board**
- 
   * **Micro USB Cable**   * **Micro USB Cable**
     * Used for UART communications JTAG programming.     * Used for UART communications JTAG programming.
 ===Software=== ===Software===
-  * **Vivado Design Suite 2015.2**+  * **Vivado Design Suite 2015.2 or newer**
  
 ---- ----
 =====Tutorial===== =====Tutorial=====
 ====1. Starting the Workshop==== ====1. Starting the Workshop====
->1.1)  +>1.1) Open the Xilinx University Program  [[https://www.xilinx.com/support/university/workshops.html | Workshops]] page in a new tab and click the **Systen Design Flow on Zynq** link. {{ :vivado:ws_zynq_1.png?772x556 }} 
->1.2)  +>1.2) Download the lab source files, which are unique to the Zybo and the Zedboard and the lab documents which are common between the two boards, under the 2015x Workshop Material section on the right. {{ :vivado:ws_zynq_2.png?772x556 }} 
->1.3) +>1.3) Follow the labs as they guide you through the system design flow for Zynq.