This workshop serves as an introduction into FPGA design flow using Vivado. It is split into six labs that explore various tools and processes in FPGA design flow.

• Lab1 has you create a simple HDL design where you'll learn how to simulate the design.

• In Lab2 you'll learn

• Lab3 builds off what you've done in Lab2 and focuses on timing analysis. You'll verify your design on your hardware at the conclusion of the lab.

• Lab4 introduces you to the IP Catolog. You'll instantiate a generated clock core for use in your design. Using the IP Integrator, you'll also learn how to generate a FIFO core for your design.

• You'll learn how to create a project using the I/O Planning tools in Lab5. Once you've defined the pin locations and have exported the project, you'll perform timing analysis on the design.

• Lab6 finsihes the workshop by teaching you how to debug your design using the Mark Debug feature and the Integrated Logic Analizer (ILA) core found in the IP Catalog.

• Experience with digital logic and FPGA design
• Familiarity with Vivado Design Software
• Basic understanding of C programming