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| vivado:ws_fpga [2016/01/21 19:54] – Andrew Holzer | vivado:ws_fpga [2022/10/04 11:38] (current) – external edit 127.0.0.1 | ||
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| + | ======System Design Flow in Vivado====== | ||
| + | {{ : | ||
| =====Overview===== | =====Overview===== | ||
| This workshop serves as an introduction into FPGA design flow using Vivado. It | This workshop serves as an introduction into FPGA design flow using Vivado. It | ||
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| ===Hardware=== | ===Hardware=== | ||
| * **Digilent Nexys Video, Nexys 4 DDR, or Basys 3 FPGA Board** | * **Digilent Nexys Video, Nexys 4 DDR, or Basys 3 FPGA Board** | ||
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| * **Micro USB Cable** | * **Micro USB Cable** | ||
| * Used for UART communications JTAG programming. | * Used for UART communications JTAG programming. | ||