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vivado:ws_fpga [2016/01/21 18:48] – Andrew Holzervivado:ws_fpga [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 +======System Design Flow in Vivado======
 +{{ :vivado:ws_fpga_3.png?416x300 }}
 =====Overview===== =====Overview=====
 This workshop serves as an introduction into FPGA design flow using Vivado. It This workshop serves as an introduction into FPGA design flow using Vivado. It
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 ===Hardware=== ===Hardware===
   * **Digilent Nexys Video, Nexys 4 DDR, or Basys 3 FPGA Board**   * **Digilent Nexys Video, Nexys 4 DDR, or Basys 3 FPGA Board**
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   * **Micro USB Cable**   * **Micro USB Cable**
     * Used for UART communications JTAG programming.     * Used for UART communications JTAG programming.
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 =====Tutorial===== =====Tutorial=====
 ====1. Starting the Workshop==== ====1. Starting the Workshop====
->1.1) Open the Xilinx University Program  {{http://www.xilinx.com/support/university/workshops.html | Workshops}} page in a new tab and click the **FPGA Design Flow using Vivado** link. {{ :vivado:ws_fpga_1.png?635x525 }}+>1.1) Open the Xilinx University Program  {{http://www.xilinx.com/support/university/workshops.html | Workshops}} page in a new tab and click the **FPGA Design Flow using Vivado** link. {{ :vivado:ws_fpga_1.png?772x556 }}
  
->1.2) Download the lab source files and the lab documents under the 2015x Workshop Material section on the right. {{ :vivado:ws_fpga_2.png?635x525 }}+>1.2) Download the lab source files and the lab documents under the 2015x Workshop Material section on the right. {{ :vivado:ws_fpga_2.png?772x556 }}
  
->1.3) Follow the labs as they guide you through FPGA design flow. {{ :vivado:ws_fpga_3.png }}+>1.3) Follow the labs as they guide you through FPGA design flow.