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vivado:ws_fpga [2015/12/14 18:22] – Andrew Holzervivado:ws_fpga [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 +======System Design Flow in Vivado======
 +{{ :vivado:ws_fpga_3.png?416x300 }}
 =====Overview===== =====Overview=====
 This workshop serves as an introduction into FPGA design flow using Vivado. It This workshop serves as an introduction into FPGA design flow using Vivado. It
 is split into six labs that explore various tools and processes in FPGA is split into six labs that explore various tools and processes in FPGA
-design flow. +design flow. The labs are as follows:
    
   * Lab1 has you create a simple HDL design where you'll learn how to simulate the design.   * Lab1 has you create a simple HDL design where you'll learn how to simulate the design.
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 ===Hardware=== ===Hardware===
   * **Digilent Nexys Video, Nexys 4 DDR, or Basys 3 FPGA Board**   * **Digilent Nexys Video, Nexys 4 DDR, or Basys 3 FPGA Board**
- 
   * **Micro USB Cable**   * **Micro USB Cable**
     * Used for UART communications JTAG programming.     * Used for UART communications JTAG programming.
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 =====Tutorial===== =====Tutorial=====
 ====1. Starting the Workshop==== ====1. Starting the Workshop====
->1.1) Open the Xilinx University Program  {{http://www.xilinx.com/support/university/workshops.html | Workshops}} page in a new tab and click the **FPGA Design Flow using Vivado** link.+>1.1) Open the Xilinx University Program  {{http://www.xilinx.com/support/university/workshops.html | Workshops}} page in a new tab and click the **FPGA Design Flow using Vivado** link. {{ :vivado:ws_fpga_1.png?772x556 }}
  
->1.2) Download the lab source files and the lab documents under the 2015x Workshop Material section on the right.+>1.2) Download the lab source files and the lab documents under the 2015x Workshop Material section on the right. {{ :vivado:ws_fpga_2.png?772x556 }}
  
->1.3) These lab documents will guide you through the FPGA design flow.+>1.3) Follow the labs as they guide you through FPGA design flow.