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vivado:library [2020/05/15 20:54] – [IPcores] Monica Ignatvivado:library [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 =====Overview===== =====Overview=====
 Vivado Library is, as its name states, a library that contains free-to-use IP cores and interface definitions compatible with Xilinx Vivado IP Catalog. Vivado Library is, as its name states, a library that contains free-to-use IP cores and interface definitions compatible with Xilinx Vivado IP Catalog.
-Due to the fact that it's a library constantly updating and changing, adding new IPs or features, it is recommended to periodically check the [[https://github.com/Digilent/vivado-library/releases|github repository]] to find the latest release.+Due to the fact that it's a library constantly updating and changing, adding new IPs or features, it is recommended to periodically check the [[https://github.com/Digilent/vivado-library/releases|Github repository's releases page]] to find the latest release.
 This GitHub repository contains a large number of IP cores intended for use with Digilent boards, including all of Digilent's Pmod IP cores and Pmod interface descriptions. This GitHub repository contains a large number of IP cores intended for use with Digilent boards, including all of Digilent's Pmod IP cores and Pmod interface descriptions.
 The version number matches the version of Vivado being used (example: "v2016.4-1" is the first release for Vivado 2016.4). The version number matches the version of Vivado being used (example: "v2016.4-1" is the first release for Vivado 2016.4).
    
 ===== Installation Guide ===== ===== Installation Guide =====
-Steps for using the Vivado Library into your projects:+Steps for including the Vivado Library in your projects:
  
-  - Download the **vivado-library-<version>.zip** file (//NOT one of the source code archives!//), then extract this archive in a location to remember. +<WRAP group> <WRAP column half> 
 +Download the **vivado-library-<version>.zip** file (//NOT one of the source code archives!//), then extract this archive in a location to remember. 
  
 Click **Project Settings** under Project Manager. Click **Project Settings** under Project Manager.
 +</WRAP> <WRAP column half>
 {{:arty:projsetting.jpg?direct&200|}} {{:arty:projsetting.jpg?direct&200|}}
 +</WRAP> </WRAP>
  
-  - Click **IP** then open the **Repository Manager** tab. Click the {{:genesys2:plus.jpg?direct|}} **Add** button and select the **vivado-library** folder from where the ZIP archive was extracted to. Click **OK**. +<WRAP group> <WRAP column half> 
- +Click **IP** then open the **Repository Manager** tab. Click the {{:genesys2:plus.jpg?direct|}} **Add** button and select the **vivado-library** folder from where the ZIP archive was extracted to. Click **OK**. 
-{{:vivado:iprepo.jpg?direct&600|}}+</WRAP> <WRAP column half> 
 +{{:vivado:iprepo.jpg?direct&400|}} 
 +</WRAP> </WRAP>
  
  
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     * [[https://github.com/Digilent/vivado-library/tree/master/ip/hls_saturation_enhance_1_0|hls_saturation_enhance_1_0]] - This IP interfaces to both Axi-Lite and Axi-Stream in order to process a video stream and control the resolution and the saturation factor. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/hls_saturation_enhance_1_0/doc/HLS_Saturation_Enhancement_v1_0.pdf|documentation]]     * [[https://github.com/Digilent/vivado-library/tree/master/ip/hls_saturation_enhance_1_0|hls_saturation_enhance_1_0]] - This IP interfaces to both Axi-Lite and Axi-Stream in order to process a video stream and control the resolution and the saturation factor. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/hls_saturation_enhance_1_0/doc/HLS_Saturation_Enhancement_v1_0.pdf|documentation]]
     * [[https://github.com/Digilent/vivado-library/tree/master/ip/rgb2dpvid_v1_0|rgb2dpvid_v1_0]] - This IP interfaces to an RGB video data bus at its inputs and outputs a video data interface of the Xilinx LogiCORE IP DisplayPort. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/rgb2dpvid_v1_0/docs/rgb2dpvid_v1_0.pdf|documentation]]     * [[https://github.com/Digilent/vivado-library/tree/master/ip/rgb2dpvid_v1_0|rgb2dpvid_v1_0]] - This IP interfaces to an RGB video data bus at its inputs and outputs a video data interface of the Xilinx LogiCORE IP DisplayPort. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/rgb2dpvid_v1_0/docs/rgb2dpvid_v1_0.pdf|documentation]]
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/rgb2dvi|rgb2dvi]] - This IP interfaces directly to raw transition-minimized differential signaling (TMDS) clock and data channel outputs as defined in DVI 1.0 specs for Source devices. It encodes 24-bit RGB video data along with the pixel clock and synchronization signals. More details about its functionality can be found in the[[https://github.com/Digilent/vivado-library/blob/master/ip/rgb2dvi/docs/rgb2dvi.pdf|documentation]]+    * [[https://github.com/Digilent/vivado-library/tree/master/ip/rgb2dvi|rgb2dvi]] - This IP interfaces directly to raw transition-minimized differential signaling (TMDS) clock and data channel outputs as defined in DVI 1.0 specs for Source devices. It encodes 24-bit RGB video data along with the pixel clock and synchronization signals. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/rgb2dvi/docs/rgb2dvi.pdf|documentation]]
     * [[https://github.com/Digilent/vivado-library/tree/master/ip/rgb2vga_v1_0|rgb2vga_v1_0]] - It accepts a Xilinx vid_io input and outputs an independently customizable color depth, properly blanked RGB pixel bus to connect to a VGA DAC. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/rgb2vga_v1_0/docs/rgb2vga_v1_0.pdf|documentation]]     * [[https://github.com/Digilent/vivado-library/tree/master/ip/rgb2vga_v1_0|rgb2vga_v1_0]] - It accepts a Xilinx vid_io input and outputs an independently customizable color depth, properly blanked RGB pixel bus to connect to a VGA DAC. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/rgb2vga_v1_0/docs/rgb2vga_v1_0.pdf|documentation]]
     * [[https://github.com/Digilent/vivado-library/tree/master/ip/usb2device_v1_0|usb2device_v1_0]] - It provides communication between an AXI Microblaze system and a USB 2.0 Host. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/usb2device_v1_0/docs/USB_Device.docx|documentation]]     * [[https://github.com/Digilent/vivado-library/tree/master/ip/usb2device_v1_0|usb2device_v1_0]] - It provides communication between an AXI Microblaze system and a USB 2.0 Host. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/usb2device_v1_0/docs/USB_Device.docx|documentation]]