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vivado:library [2020/05/15 20:22] – [IPcores] Monica Ignatvivado:library [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 =====Overview===== =====Overview=====
 Vivado Library is, as its name states, a library that contains free-to-use IP cores and interface definitions compatible with Xilinx Vivado IP Catalog. Vivado Library is, as its name states, a library that contains free-to-use IP cores and interface definitions compatible with Xilinx Vivado IP Catalog.
-Due to the fact that it's a library constantly updating and changing, adding new IPs or features, it is recommended to periodically check the [[https://github.com/Digilent/vivado-library/releases|github repository]] to find the latest release.+Due to the fact that it's a library constantly updating and changing, adding new IPs or features, it is recommended to periodically check the [[https://github.com/Digilent/vivado-library/releases|Github repository's releases page]] to find the latest release.
 This GitHub repository contains a large number of IP cores intended for use with Digilent boards, including all of Digilent's Pmod IP cores and Pmod interface descriptions. This GitHub repository contains a large number of IP cores intended for use with Digilent boards, including all of Digilent's Pmod IP cores and Pmod interface descriptions.
 The version number matches the version of Vivado being used (example: "v2016.4-1" is the first release for Vivado 2016.4). The version number matches the version of Vivado being used (example: "v2016.4-1" is the first release for Vivado 2016.4).
    
 ===== Installation Guide ===== ===== Installation Guide =====
-Steps for using the Vivado Library into your projects:+Steps for including the Vivado Library in your projects:
  
-  - Download the **vivado-library-<version>.zip** file (//NOT one of the source code archives!//), then extract this archive in a location to remember. +<WRAP group> <WRAP column half> 
 +Download the **vivado-library-<version>.zip** file (//NOT one of the source code archives!//), then extract this archive in a location to remember. 
  
 Click **Project Settings** under Project Manager. Click **Project Settings** under Project Manager.
 +</WRAP> <WRAP column half>
 {{:arty:projsetting.jpg?direct&200|}} {{:arty:projsetting.jpg?direct&200|}}
 +</WRAP> </WRAP>
  
-  - Click **IP** then open the **Repository Manager** tab. Click the {{:genesys2:plus.jpg?direct|}} **Add** button and select the **vivado-library** folder from where the ZIP archive was extracted to. Click **OK**. +<WRAP group> <WRAP column half> 
- +Click **IP** then open the **Repository Manager** tab. Click the {{:genesys2:plus.jpg?direct|}} **Add** button and select the **vivado-library** folder from where the ZIP archive was extracted to. Click **OK**. 
-{{:vivado:iprepo.jpg?direct&600|}}+</WRAP> <WRAP column half> 
 +{{:vivado:iprepo.jpg?direct&400|}} 
 +</WRAP> </WRAP>
  
  
 ===== IPcores ===== ===== IPcores =====
  
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/AXI_DPTI_1.0|AXI_DPTI_1.0]] - this core implements an interface between DPTI and  +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/AXI_DPTI_1.0|AXI_DPTI_1.0]] - this core implements an interface between DPTI and AXI4 Stream. The interface will be controlled using Microblaze via control and status registers and it will theoretically be capable of speeds up to 480 megabits per second. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-  
-    AXI4 Stream. This interface will be controlled using Microblaze via control and status registers and it will theoretically be capable of  +library/blob/master/ip/AXI_DPTI_1.0/doc/AXI%20DPTI.pdf|documentation]] 
-    speeds up to 480 megabits per second. +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/MIPI_CSI_2_RX|MIPI_CSI_2_RX]] - This IP is compatible with CSI-2 1.0 specifications and supports decoding selected pixel formats and packing data into an AXI-Stream. It pairs up with a MIPI D-PHY Receiver IP over the standard PHY Protocol Interface (PPI) to source a video subsystem. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/MIPI_CSI_2_RX/docs/mipi_csi_2_rx.pdf|documentation]] 
-    More details about its functionality can be found in the [[https://github.com/Digilent/vivado-  +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/MIPI_D_PHY_RX|MIPI_D_PHY_RX]] - This IP is compatible with D-PHY 1.0 specifications and serves as the lowest layer of the high-speed source-synchronous interface defined by MIPI Alliance. It pairs up with a MIPI CSI-2 Receiver IP over the standard PHY Protocol Interface (PPI) to receive data from an image sensor and source a video subsystem. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/MIPI_D_PHY_RX/docs/mipi_d_phy_rx.pdf|documentation]]
-    library/blob/master/ip/AXI_DPTI_1.0/doc/AXI%20DPTI.pdf|documentation]] +
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/MIPI_CSI_2_RX|MIPI_CSI_2_RX]] - This IP is compatible with CSI-2 1.0  +
-    specifications and supports decoding selected pixel formats and packing data into an AXI-Stream. It pairs up with a MIPI D-PHY Receiver IP  +
-    over the standard PHY Protocol Interface (PPI) to source a video subsystem. +
-    More details about its functionality can be found in the [[https://github.com/Digilent/vivado-  +
-    library/blob/master/ip/MIPI_CSI_2_RX/docs/mipi_csi_2_rx.pdf|documentation]] +
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/MIPI_D_PHY_RX|MIPI_D_PHY_RX]] - This IP is compatible with D-PHY 1.0  +
-    specifications and serves as the lowest layer of the high-speed source-synchronous interface defined by MIPI Alliance. It pairs up with a MIPI  +
-    CSI-2 Receiver IP over the standard PHY Protocol Interface (PPI) to receive data from an image sensor and source a video subsystem.  +
-    More details about its functionality can be found in the [[https://github.com/Digilent/vivado-  +
-    library/blob/master/ip/MIPI_D_PHY_RX/docs/mipi_d_phy_rx.pdf|documentation]]+
     * [[https://github.com/Digilent/vivado-library/tree/master/ip/MotorFeedback_1.0|MotorFeedback_1.0]]      * [[https://github.com/Digilent/vivado-library/tree/master/ip/MotorFeedback_1.0|MotorFeedback_1.0]] 
     * [[https://github.com/Digilent/vivado-library/tree/master/ip/PWM_1.0|PWM_1.0]]     * [[https://github.com/Digilent/vivado-library/tree/master/ip/PWM_1.0|PWM_1.0]]
     * [[https://github.com/Digilent/vivado-library/tree/master/ip/PWM_2.0|PWM_2.0]]     * [[https://github.com/Digilent/vivado-library/tree/master/ip/PWM_2.0|PWM_2.0]]
     * [[https://github.com/Digilent/vivado-library/tree/master/ip/PWM_Analyzer_1.0|PWM_Analyzer_1.0]]      * [[https://github.com/Digilent/vivado-library/tree/master/ip/PWM_Analyzer_1.0|PWM_Analyzer_1.0]] 
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/Pmods|Pmods]] - it contains a set of IPs for most of the Digilent Pmods +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/Pmods|Pmods]] - It contains a set of IPs for most of the Digilent Pmods 
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/Sync_v1_0|Sync_v1_0]] - This IP provides clock domain crossing for signals where  +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/Sync_v1_0|Sync_v1_0]] - It provides clock domain crossing for signals where variable crossing latency does not affect functionality. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/Sync_v1_0/docs/Sync_v1_0.pdf|documentation]] 
-    variable crossing latency does not affect functionality.   +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/Zmods|Zmods]] - It contains a set of low level controller for both ZmodADC1410 and ZmodDAC1411, as well as their corresponding AXI interface adapters.
-    More details about its functionality can be found in the [[https://github.com/Digilent/vivado-  +
-    library/blob/master/ip/Sync_v1_0/docs/Sync_v1_0.pdf|documentation]] +
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/Zmods|Zmods]] - it contains a set of low level controller for both ZmodADC1410  +
-    and ZmodDAC1411, as well as their corresponding AXI interface adapters.+
     * [[https://github.com/Digilent/vivado-library/tree/master/ip/axi_dynclk_v1_1|axi_dynclk_v1_1]]     * [[https://github.com/Digilent/vivado-library/tree/master/ip/axi_dynclk_v1_1|axi_dynclk_v1_1]]
     * [[https://github.com/Digilent/vivado-library/tree/master/ip/axi_i2s_adi_1.2|axi_i2s_adi_1.2]]     * [[https://github.com/Digilent/vivado-library/tree/master/ip/axi_i2s_adi_1.2|axi_i2s_adi_1.2]]
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/axi_ps2_1.0|axi_ps2_1.0]] - The purpose of this IP is to implement a software controllable PS/2 host controller. +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/axi_ps2_1.0|axi_ps2_1.0]] - The purpose of this IP is to implement a software controllable PS/2 host controller. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/axi_ps2_1.0/doc/AXI%20PS2.pdf|documentation]]
-More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/axi_ps2_1.0/doc/AXI%20PS2.pdf|documentation]]+
     * [[https://github.com/Digilent/vivado-library/tree/master/ip/clock_forwarder|clock_forwarder]]     * [[https://github.com/Digilent/vivado-library/tree/master/ip/clock_forwarder|clock_forwarder]]
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/dvi2rgb|dvi2rgb]] - This IP interfaces directly to raw transition-minimized differential signaling (TMDS) clock and data channel inputs as defined in DVI 1.0 specs for Sink devices. It decodes the video stream and outputs 24-bit RGB video data along with the pixel clock and synchronization signals recovered from the TMDS link. +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/dvi2rgb|dvi2rgb]] - This IP interfaces directly to raw transition-minimized differential signaling (TMDS) clock and data channel inputs as defined in DVI 1.0 specs for Sink devices. It decodes the video stream and outputs 24-bit RGB video data along with the pixel clock and synchronization signals recovered from the TMDS link. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/dvi2rgb/docs/dvi2rgb.pdf|documentation]] 
-More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/dvi2rgb/docs/dvi2rgb.pdf|documentation]] +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/hls_contrast_stretch_1_0|hls_contrast_stretch_1_0]] - The IP interfaces to both Axi-Lite and Axi-Stream in order to process a video stream and control the resolution and the contrast factor. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/hls_contrast_stretch_1_0/doc/HLS_Contrast_Stretch_v1_0.pdf|documentation]] 
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/hls_contrast_stretch_1_0|hls_contrast_stretch_1_0]] - This IP interfaces to both the Axi-Lite and Axi-Stream in order to process a video stream and control the resolution and the contrast factor. +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/hls_gamma_correction_1_0|hls_gamma_correction_1_0]] - The IP interfaces to both Axi-Lite and Axi-Stream in order to process a video stream and control the resolution and the gamma factor. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/hls_gamma_correction_1_0/doc/HLS_Gamma%20Correction_v1_0.pdf|documentation]] 
-More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/hls_contrast_stretch_1_0/doc/HLS_Contrast_Stretch_v1_0.pdf|documentation]] +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/hls_saturation_enhance_1_0|hls_saturation_enhance_1_0]] - This IP interfaces to both Axi-Lite and Axi-Stream in order to process a video stream and control the resolution and the saturation factor. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/hls_saturation_enhance_1_0/doc/HLS_Saturation_Enhancement_v1_0.pdf|documentation]] 
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/hls_gamma_correction_1_0|hls_gamma_correction_1_0]] - This IP interfaces to both the Axi-Lite and Axi-Stream in order to process a video stream and control the resolution and the gamma factor. +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/rgb2dpvid_v1_0|rgb2dpvid_v1_0]] - This IP interfaces to an RGB video data bus at its inputs and outputs a video data interface of the Xilinx LogiCORE IP DisplayPort. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/rgb2dpvid_v1_0/docs/rgb2dpvid_v1_0.pdf|documentation]] 
-More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/hls_gamma_correction_1_0/doc/HLS_Gamma%20Correction_v1_0.pdf|documentation]] +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/rgb2dvi|rgb2dvi]] - This IP interfaces directly to raw transition-minimized differential signaling (TMDS) clock and data channel outputs as defined in DVI 1.0 specs for Source devices. It encodes 24-bit RGB video data along with the pixel clock and synchronization signals. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/rgb2dvi/docs/rgb2dvi.pdf|documentation]] 
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/hls_saturation_enhance_1_0|hls_saturation_enhance_1_0]] - This IP interfaces to both the Axi-Lite and Axi-Stream in order to process a video stream and control the resolution and the saturation factor. +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/rgb2vga_v1_0|rgb2vga_v1_0]] - It accepts a Xilinx vid_io input and outputs an independently customizable color depth, properly blanked RGB pixel bus to connect to a VGA DAC. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/rgb2vga_v1_0/docs/rgb2vga_v1_0.pdf|documentation]] 
-More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/hls_saturation_enhance_1_0/doc/HLS_Saturation_Enhancement_v1_0.pdf|documentation]] +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/usb2device_v1_0|usb2device_v1_0]] - It provides communication between an AXI Microblaze system and a USB 2.0 Host. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/usb2device_v1_0/docs/USB_Device.docx|documentation]] 
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/rgb2dpvid_v1_0|rgb2dpvid_v1_0]] - This IP interfaces to an RGB video data bus at its inputs and outputs a video data interface of the Xilinx LogiCORE IP DisplayPort. +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/video_scaler|video_scaler]] - This IP takes video frames of arbitrary resolution over a slave AXI-Stream interface, resizes them to an arbitrary output resolution and outputs on a master AXI-Stream interface. It has an AXI4-Lite interface for control. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/video_scaler/doc/video_scaler.pdf|documentation]]
-More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/rgb2dpvid_v1_0/docs/rgb2dpvid_v1_0.pdf|documentation]] +
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/rgb2dvi|rgb2dvi]] - This IP interfaces directly to raw transition-minimized differential signaling (TMDS) clock and data channel outputs as defined in DVI 1.0 specs for Source devices. It encodes 24-bit RGB video data along with the pixel clock and synchronization signals. +
-More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/rgb2dvi/docs/rgb2dvi.pdf|documentation]] +
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/rgb2vga_v1_0|rgb2vga_v1_0]] - This IP accepts a Xilinx vid_io input and outputs an independently customizable color depth, properly blanked RGB pixel bus to connect to a VGA DAC.  +
-More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/rgb2vga_v1_0/docs/rgb2vga_v1_0.pdf|documentation]] +
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/usb2device_v1_0|usb2device_v1_0]] - This IP is designed to provide communication between an AXI Microblaze system and a USB 2.0 Host. +
-More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/usb2device_v1_0/docs/USB_Device.docx|documentation]] +
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/video_scaler|video_scaler]] - This IP takes video frames of arbitrary resolution over a slave AXI-Stream interface, resizes them to an arbitrary output resolution and outputs on a master AXI-Stream interface. It has an AXI4-Lite interface for control. +
-More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/video_scaler/doc/video_scaler.pdf|documentation]]+
 ===== Interfaces ===== ===== Interfaces =====