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vivado:getting_started_with_zynq:start [2017/09/27 22:54] – Arthur Brownvivado:getting_started_with_zynq:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
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-=== Warning === +=== Important! === 
-This page is a work in progress.+This guide is obsolete, the updated guide can be found [[:vivado:getting-started-with-ipi:start|here]].
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 +{{:vivado:getting_started_with_zynq:zynq-gsg-action.png?800|}}
  
 ===== Prerequisites ===== ===== Prerequisites =====
-  * Vivado Installed +  * A Vivado installation. See [[learn:software:tutorials:vivado-install-guide:|this tutorial]]. 
-  * Familiarity with Vivado +  * Basic familiarity with Vivado. See [[:vivado:getting_started:|this tutorial]]. 
-  * Digilent Board Files+  * Digilent Board Files installed to make selection of a target board and configuration of the Zynq IP block easier. See [[software:vivado:board-files#installation|this tutorial]]. 
 +  * A Digilent Zynq Development Board to run the project on.
  
 ===== Introduction ===== ===== Introduction =====
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 === 2.2 === === 2.2 ===
-In the dialog box, give the block design a name and a directory location to be stored in. Make sure that //Specify source set// is set to //Design Sources//.+In the dialog box, give the block design a name. The directory location is where the block design will be stored, this can be changed, but it is recommended to leave it as //<Local to Project>//. Make sure that //Specify source set// is set to //Design Sources//.
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 === Important === === Important ===
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 ==== 3. IP Integrator Tools ==== ==== 3. IP Integrator Tools ====
  
-There are many tools and places to find information available for use in the IP Integrator, this section will describe some of the most important ones.+As a general overview, Zynq designs consist of two areas, the processor, and the FPGA. The processor has some additional hardware surrounding it, and connects to other peripherals on the board that are not part of the Zynq chip. The FPGA also connects to other on board hardware. The communications protocol used to move data between the FPGA and processor, as well as between pieces of the FPGA, is called AXI. 
 + 
 +Each AXI peripheral programmed onto the FPGA will be assigned an area of the Zynq's memory space that will be used to address each of its control registers. Adding a simple AXI interface to a design will require the addition of two new blocks, the AXI Interconnect, which defines how the signals are routed, and the reset controller, which will connect a processor reset to the resets of each AXI block and the interface. 
 + 
 +Much of basic Zynq design consists of connecting different AXI peripherals to the processor, clocking them appropriately, and using them to control off-chip devices. 
 + 
 +With this context out of the way, many of the tools that can be used to create a design in Zynq will be described.
  
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   * //Optimize Routing// ({{:vivado:getting_started_with_zynq:buttons:optimize-routing.png|}}) tells Vivado to visually clean up the block design by only rerouting signals.   * //Optimize Routing// ({{:vivado:getting_started_with_zynq:buttons:optimize-routing.png|}}) tells Vivado to visually clean up the block design by only rerouting signals.
   * //Show Interface Connections Only// ({{:vivado:getting_started_with_zynq:buttons:show-interface-connections-only.png|}}) hides clock and reset signals, only useful for highly complex designs.   * //Show Interface Connections Only// ({{:vivado:getting_started_with_zynq:buttons:show-interface-connections-only.png|}}) hides clock and reset signals, only useful for highly complex designs.
 +
 +Additionally, changes to the design can be made by interacting directly with the Diagram pane's graphical interface. Objects can be moved by clicking and dragging them. Connections can be made by hovering over a port until the pencil cursor ({{:vivado:getting_started_with_zynq:pencil.png|}}) appears, then drawing a line to another port, pin, or wire.
  
 With a general understanding of the actions that can be taken in the IPI, a design can now be created. With a general understanding of the actions that can be taken in the IPI, a design can now be created.
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 === 4.2 === === 4.2 ===
-Before doing anything else, select //Run Block Automation// in the green tab at the top of the Block Design screen. This button launches a dialog that will add several important required connections for the processor.+Before doing anything else, select //Run Block Automation// in the green tab at the top of the block design //Diagram// pane. This button launches a dialog that will add several important required connections for the processor.
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-=== 5.9 === 
 Since the target design for this guide requires no major changes to the Zynq block's configuration, select //Cancel// or click the 'X' to close the dialog. Changes are not saved except when //Apply// or //Finish// is selected. Since the target design for this guide requires no major changes to the Zynq block's configuration, select //Cancel// or click the 'X' to close the dialog. Changes are not saved except when //Apply// or //Finish// is selected.
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 ==== 6. Add Peripherals ==== ==== 6. Add Peripherals ====
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 === 6.1 === === 6.1 ===
-In the //Board// tab to the left of the window, right click on //RGB LEDs// and select //Connect Board Component//. If the board does not have RGB LEDs, use the normal LEDs instead.+In the //Board// tab to the left of the diagram pane, right click on //RGB LEDs// and select //Connect Board Component//. If the board does not have RGB LEDs, use the normal LEDs instead.
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 === 6.3 === === 6.3 ===
-This will place a general purpose input/output controller into the block design. Required configuration settings for the size of the GPIO channel will already be done, but additional options, like creating an interrupt port, or adding a second channel can be enabled by configuring the IP. The IP can be customized by double clicking on it, or by selecting it and clicking the //Customize Block// button ({{:vivado:getting_started_with_zynq:buttons:customize-block.png|}}).+This will place a general purpose input/output (GPIO) controller into the block design. Required configuration settings for the size of the GPIO channel will already be done, but additional options, like creating an interrupt port, or adding a second channel can be enabled by configuring the IP. The IP can be customized by double clicking on it, or by selecting it and clicking the //Customize Block// button ({{:vivado:getting_started_with_zynq:buttons:customize-block.png|}}).
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-vivado:getting_started_with_zynq:buttons:run-connection.png?500 |}}+{{ :vivado:getting_started_with_zynq:buttons:run-connection.png?500 |}}
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 === 7.2 === === 7.2 ===
-Make sure that the axi_gpio_0 block is checked in the menu to the left. Several options are present here, including the clock that the AXI Interface will run off of.+Make sure that the axi_gpio_0 block is checked in the menu to the left. Several options are present here, including the a drop-down to select the clock that the AXI Interface will run off of - keep this field as //Auto// to let Vivado pick.
  
 Click //Finish// to generate the AXI connection and its related blocks. Click //Finish// to generate the AXI connection and its related blocks.
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- 
-AXI is the communications protocol that is used by the Zynq processor to communicate with each of the peripheral controllers in the design. Each peripheral will be assigned an area of the Zynq's memory space that will be used to address each of its controller's registers. Adding a simple AXI interface to a design will require the addition of two new blocks, the AXI Interconnect, which defines how the signals are routed, and the reset controller, which will connect a processor reset to the resets of each AXI block and the interface. 
  
 ==== 8. Generate the Bitstream ==== ==== 8. Generate the Bitstream ====
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 === 8.3 === === 8.3 ===
-With a validated design and a top module, a bitstream can now be generated. The Getting Started with Vivado guide explains this process in a little more detail, but for now, click the //Generate Bitstream// button in the //Flow Navigator//.+With a validated design and a top module, a bitstream can now be generated. The [[:vivado:getting_started:|Getting Started with Vivado]] guide explains this process in a little more detail, but for now, click the //Generate Bitstream// button in the //Flow Navigator//.
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 === 10.3 === === 10.3 ===
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 In the New Project dialog, give the project a name, and make sure that //C// is selected as the //Language// in the //Target Software// box. In the New Project dialog, give the project a name, and make sure that //C// is selected as the //Language// in the //Target Software// box.
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 === Important === === Important ===
-Do NOT use spaces in the export location path. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]].+Do NOT use spaces in the project name. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]].
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 Click //Next// to continue. Click //Next// to continue.
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 {{ :vivado:getting_started_with_zynq:sdk-dialog-new-project.png?500 |}} {{ :vivado:getting_started_with_zynq:sdk-dialog-new-project.png?500 |}}
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 === 11.2 === === 11.2 ===
 +Leave all of the settings in the Program FPGA dialog as they are, then click //Program//. This only programs the FPGA, not the processor, so that is next.
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 === 11.3 === === 11.3 ===
 +Right click on the application project in the //Project Explorer//, then select //Run As > Launch on Hardware (System Debugger)//.
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