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This shows you the differences between two versions of the page.
| vivado:getting_started:start [2020/03/17 00:04] – [6. Adding a Constraint File] Arthur Brown | vivado:getting_started:start [2022/10/04 11:38] (current) – external edit 127.0.0.1 | ||
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| Line 148: | Line 148: | ||
| * Tools for creating Block Designs | * Tools for creating Block Designs | ||
| * // | * // | ||
| - | * Allows a developer to verify the output of their deisgn | + | * Allows a developer to verify the output of their design |
| * //RTL Analysis// | * //RTL Analysis// | ||
| * lets the developer see how the tools are interpreting their code | * lets the developer see how the tools are interpreting their code | ||
| Line 259: | Line 259: | ||
| ==== 6. Adding a Constraint File ==== | ==== 6. Adding a Constraint File ==== | ||
| - | In order to connect HDL code with the physical pins of the FPGA, a constraint file needs to be added or created. Digilent has produced a Xilinx Design Constraint (XDC) file for each of our boards. Download | + | In order to connect HDL code with the physical pins of the FPGA, a constraint file needs to be added or created. Digilent has produced a Xilinx Design Constraint (XDC) file for each of our boards. Download [[https:// |
| <WRAP group> | <WRAP group> | ||
| Line 510: | Line 510: | ||
| You should now see one of the LEDs on your board blinking! | You should now see one of the LEDs on your board blinking! | ||
| - | Be sure to visit your board' | + | Be sure to visit your board' |
| - | {{tag> | + | {{tag> |

