Differences

This shows you the differences between two versions of the page.

Link to this comparison view

vivado:getting_started:start [2017/09/14 20:03] – Arthur Brownvivado:getting_started:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
Line 1: Line 1:
 ====== Getting Started with Vivado ====== ====== Getting Started with Vivado ======
 ----- -----
- 
-===== Prerequisites ===== 
-Prior to starting this guide make sure to install Vivado. For more information see our [[learn:software:tutorials:vivado-install-guide:|Installing Vivado]] guide. 
- 
-Make sure to install [[reference:software:vivado:board-files#installation|Digilent's board files]] to make selection of a target board easier. 
  
 ===== Introduction ===== ===== Introduction =====
Line 13: Line 8:
 The goal of this guide is to familiarize the reader with the Vivado tools through the hello world of hardware, blinking an LED. The goal of this guide is to familiarize the reader with the Vivado tools through the hello world of hardware, blinking an LED.
  
-This guide was created using Vivado 2016.4. +**Note:** //While this guide was created using Vivado 2016.4, the workflow described has not substantially changed, and the guide works as described through Vivado 2019.2, the latest version as of time of writing.// 
-==== 1. Starting Vivado ====+ 
 +---- 
 +===== Prerequisites ===== 
 +Prior to starting this guide make sure to install Vivado: 
 +  * For versions 2019.2 and later, see [[vivado:installing-vivado:v2019.2]]. 
 +  * For versions prior to 2019.2, see [[vivado:installing-vivado:start]]. 
 + 
 +---- 
 +===== Guide ===== 
 +==== 1. Launching Vivado ====
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
Line 28: Line 32:
 <WRAP column half> <WRAP column half>
 **Linux**\\ **Linux**\\
-Open a Terminal and run+Open a terminal, cd into a working directory that can be cluttered with temporary Vivado files and logs, then run the following:
 <code>source <install_path>/Vivado/<version>/settings64.sh && vivado</code> <code>source <install_path>/Vivado/<version>/settings64.sh && vivado</code>
 </WRAP> </WRAP>
Line 39: Line 43:
 This is the screen that displays after Vivado starts up. The buttons are described below using the image as a guide. This is the screen that displays after Vivado starts up. The buttons are described below using the image as a guide.
  
-{{ :vivado:getting_started:v2016.4:vivado-home-outline.jpg?direct&500 |}}+{{ :vivado:getting_started:v2016.4:vivado-home-outline.jpg?direct&800 |}}
  
 == 1. Create New Project == == 1. Create New Project ==
Line 47: Line 51:
 == 2. Open Project == == 2. Open Project ==
  
-This button will open a file browser. Navigate to the desired XPR file and click //Open// to open the project in Vivado.+This button will open a file browser. Navigate to the desired Xilinx Project (.xpr) file and click //Open// to open the project in Vivado.
  
 == 3. Open Example Project == == 3. Open Example Project ==
Line 55: Line 59:
 == 4. Open Hardware Manager == == 4. Open Hardware Manager ==
  
-This will open the Hardware Manager without an associated project. If connecting to and programming a device is all that is required by the user this is the button to use.+This will open the Hardware Manager without an associated project. If connecting to and programming a device is all that is required by the user, then this is the button to use.
  
 ==== 3. Creating a New Project ==== ==== 3. Creating a New Project ====
Line 72: Line 76:
 <WRAP column half> <WRAP column half>
 === 3.2 === === 3.2 ===
-The text in the dialog describes the steps that will be taken to create a project. Click //Next// to continue to the first step.+The text in this dialog describes the steps that will be taken to create a project. Click //Next// to continue to the first step.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 97: Line 101:
 <WRAP column half> <WRAP column half>
 === 3.4 === === 3.4 ===
-Now that the project has a name and a place to save its files we need to select the type of project we will be creating. Select //RTL Project// and make sure to check //Do not specify sources at this time//. We will add and create source files once the project has been created. Advanced users may use the other options on this screen, but we will not be covering them in this guide.+Now that the project has a name and a place to save its files we need to select the type of project we will be creating. Select //RTL Project// and make sure to check //Do not specify sources at this time//. Source files will be added and created after the project has been created. Advanced users may use the other options on this screen, but they will not be covered in this guide.
  
 Click //Next// to continue. Click //Next// to continue.
Line 111: Line 115:
 <WRAP round center important> <WRAP round center important>
 === Important === === Important ===
-If you haven't yet installed Digilent's board files, you will need to revisit the prerequisites section of this guide, and then close start again from the beginning. +If your board does not appear in this list, then Digilent's board files haven't yet been installed. If this is the case, revisit the prerequisites section of this guide, then close Vivado and start again from the beginning.
 </WRAP> </WRAP>
 Now it is time to choose the target device. Click the //Boards// tab at the top of the dialog, then select your board from the list. Now it is time to choose the target device. Click the //Boards// tab at the top of the dialog, then select your board from the list.
Line 136: Line 140:
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-The Flow Navigator is the most important pane of the main Vivado window to know. It is how a user navigates between different Vivado tools.+The //Flow Navigator// is the most important pane of the main Vivado window to know. It is how a user navigates between different Vivado tools.
  
 The Navigator is broken into seven sections: The Navigator is broken into seven sections:
Line 144: Line 148:
     * Tools for creating Block Designs     * Tools for creating Block Designs
   * //Simulation//   * //Simulation//
-    * Allows a developer to verify the output of their deisgn prior to programming their device+    * Allows a developer to verify the output of their design prior to programming their device
   * //RTL Analysis//   * //RTL Analysis//
     * lets the developer see how the tools are interpreting their code     * lets the developer see how the tools are interpreting their code
Line 172: Line 176:
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-The Project Manager consists of four panes, Sources, Properties, Results, and the Workspace.+The //Project Manager// consists of four panes, //Sources//, //Properties//, //Results//, and the //Workspace//.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 181: Line 185:
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-The Sources pane contains the project hierarchy and is used for opening up files. The folder structure is organized such that the HDL files are kept under the //Design Sources// folder, constraints are kept under the //Constraints// folder, and simulation files are kept under the //Simulation Sources// folder. Files can be opened in the Workspace by double-clicking on the corresponding entry in the Sources pane. Sources can also be added by either right clicking the folder to add the file to and selecting //Add Sources// or by clicking the //Add Sources// button ({{:vivado:getting_started:add_sources_btn.png?nolink}}).+The //Sources// pane contains the project hierarchy and is used for opening up files. The folder structure is organized such that the HDL files are kept under the //Design Sources// folder, constraints are kept under the //Constraints// folder, and simulation files are kept under the //Simulation Sources// folder. Files can be opened in the Workspace by double-clicking on the corresponding entry in the Sources pane. Sources can also be added by either right clicking the folder to add the file to and selecting //Add Sources// or by clicking the //Add Sources// button ({{:vivado:getting_started:add_sources_btn.png?nolink}}).
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 190: Line 194:
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-The Properties pane allows for viewing and editing of file properties. When a file is selected in the Sources pane its properties are shown in here. This pane can usually be ignored.+The //Properties// pane allows for viewing and editing of file properties. When a file is selected in the Sources pane its properties are shown in here. This pane can usually be ignored.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 199: Line 203:
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-The unnamed pane at the bottom of the Project Manager window consists of several different useful tools for debugging a project. The most important one to know is the Messages tool. This tool parses the Tcl console for errors, warnings, and other important information and displays it in an informative way.+The unnamed pane at the bottom of the Project Manager window consists of several different useful tools for debugging a project. The most important one to know is the //Messages// tool. This tool parses the Tcl console for errors, warnings, and other important information and displays it in an informative way.
  
 These tools can be accessed by selecting the different tabs at the bottom of this pane. These tools can be accessed by selecting the different tabs at the bottom of this pane.
Line 210: Line 214:
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-The Tcl Console is a tool that allows for running commands directly without the use of the main user interface. Some messages may link to the Tcl Console to provide more information regarding an error.+The //Tcl Console// is a tool that allows for running commands directly without the use of the main user interface. Some messages may link to the Tcl Console to provide more information regarding an error.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 219: Line 223:
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-The Reports tool is useful for quickly jumping to any one of the many reports that Vivado generates on a design. These reports include power, timing, and utilization just to name a few.+The //Reports// tool is useful for quickly jumping to any one of the many reports that Vivado generates on a design. These reports include power, timing, and utilization just to name a few.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 228: Line 232:
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-The Log displays the output from the latest Synthesis, Implementation, and Simulation runs. Digging into this is usually not necessary as the reports and messages view store the information in the log in a more readable format.+The //Log// displays the output from the latest Synthesis, Implementation, and Simulation runs. Digging into this is usually not necessary as the reports and messages view store the information in the log in a more readable format.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 237: Line 241:
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-The last tool is the Design Runs. Using this tool run settings can be edited and new runs can be created. This tool is useful when targeting multiple devices with the same design.+The last tool is the //Design Runs//. Using this tool run settings can be edited and new runs can be created. This tool is useful when targeting multiple devices with the same design.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 246: Line 250:
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-The most important pane in the Project Manager is the Workspace. The Workspace is where reports are opened for viewing and HDL/constraints files are opened for editing. Initially the Workspace displays the Project Summary which show some basic information from some of the reports.+The most important pane in the Project Manager is the //Workspace//. The Workspace is where reports are opened for viewing and HDL/constraints files are opened for editing. Initially the Workspace displays the //Project Summary// which show some basic information from some of the reports.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 255: Line 259:
 ==== 6. Adding a Constraint File ==== ==== 6. Adding a Constraint File ====
  
-In order to connect our HDL code with the physical pins of the FPGA, we need to add or create a constraint file. Digilent has produced a Xilinx Design Constraint (XDC) file for each of our boards. Download the [[https://github.com/Digilent/digilent-xdc/archive/master.zip|ZIP Archive]] containing each of these master XDC files, then extract it in a location you will remember.+In order to connect HDL code with the physical pins of the FPGA, a constraint file needs to be added or created. Digilent has produced a Xilinx Design Constraint (XDC) file for each of our boards. Download [[https://github.com/Digilent/digilent-xdc/archive/master.zip|digilent-xdc-master.zip]], the ZIP Archive containing each of these master XDC files, then extract it in a location you will remember.
  
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
 === 6.1 === === 6.1 ===
-In the Project Manager section of the Flow Navigator, click the {{:vivado:getting_started:v2016.4:sources:add-sources.png}} button. In the wizard that pops up, select //Add or create constraints// then click //Next//.+In the //Project Manager// section of the //Flow Navigator//, click the {{:vivado:getting_started:v2016.4:sources:add-sources.png}} button. In the wizard that pops up, select //Add or create constraints// then click //Next//.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 270: Line 274:
 <WRAP column half> <WRAP column half>
 === 6.2 === === 6.2 ===
-At this stage, we will be provided a list of all of the constraint files that will be added or created when we click Finish. Currently this list is empty, this will change when we have added or created files. We will not be creating a constraint file from scratch in this guide, so click //Add Files//.+At this stage, Vivado provides a list of all of the constraint files that will be added or created when we click Finish. Currently this list is empty, this will change when files have been added or created. A constraint file will not be created from scratch in this guide, so click //Add Files//.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 292: Line 296:
 <WRAP column half> <WRAP column half>
 === 6.4 === === 6.4 ===
-Make sure that your XDC file has been added into the list of sources, then click //Finish//.+Make sure that the selected XDC file has been added into the list of sources, and that the //Copy constraint files into project// is checked, then click //Finish//. 
 + 
 +**Note:** //Leaving the Copy... box unchecked means that any editing done to the constraint file will be reflected in the original copy. Checking the box is highly recommended//
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 301: Line 307:
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-In the sources pane, expand the constraints directory, then double click on the constraints file you just added. Each of Digilent's XDC files contains constraints for each of the commonly used peripherals on their respective boards. For this demo, we need the default system clock and a single led.+In the //Sources// pane of the //Project Manager//, expand the //Constraints// folder, then double click on the XDC file you just added. Each of Digilent's XDC files contains constraints for each of the commonly used peripherals on their respective boards. For this demo, constraining the default system clock and a single led is required.
  
-Find and uncomment the lines corresponding to the ports led[0] and clk by removing the '#' symbol at the beginning of the line. On some boards the clock port will consist of two different ports, clk_p and clk_n. Uncomment the create_clock line that follows the clock port/s definition as well.+Find and uncomment the lines that call //get_ports// on the names led[0] and clk by removing the '#' symbol at the beginning of the line. On some boards the clock port will consist of two different ports, clk_p and clk_n. The clock port is occasionally named something like sysclk, but should appear at the top of the XDC file. Uncomment the //create_clock// line that follows the clock port/s definition as well.
 <WRAP round center tip> <WRAP round center tip>
 === Tip === === Tip ===
Line 320: Line 326:
 <WRAP column half> <WRAP column half>
 === 7.1 === === 7.1 ===
-In the Project Manager section of the Flow Navigator, click the {{:vivado:getting_started:v2016.4:sources:add-sources.png}} button again. Select //Add or create design sources// then click //Next//.+In the //Project Manager// section of the //Flow Navigator//, click the {{:vivado:getting_started:v2016.4:sources:add-sources.png}} button again. Select //Add or create design sources// then click //Next//.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
-FIXME+{{ :vivado:getting_started:v2016.4:sources:create-source-1.png?direct&500 |}}
 </WRAP> </WRAP>
 </WRAP> </WRAP>
Line 344: Line 350:
 <WRAP column half> <WRAP column half>
 === 7.3 === === 7.3 ===
-You will be prompted to select a File type, name, and location for your file. Make sure to pick //Verilog// and //<Local to project>// for the type and location. Give your file a name ending in '.v'.+You will be prompted to select a //File type//, //File name//, and //File location//. Make sure to pick //Verilog// and //<Local to project>// for the type and location. Give your file a name ending in '.v'.
 <WRAP center round important> <WRAP center round important>
 === Important === === Important ===
Line 359: Line 365:
 <WRAP column half> <WRAP column half>
 === 7.4 === === 7.4 ===
-Make sure that your new file has been added into the list of sources, then click //Finish//.+Make sure that the new Verilog source file has been added into the list of sources, then click //Finish//.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 366: Line 372:
 </WRAP> </WRAP>
  
-<WRAP group> 
-<WRAP column half> 
-</WRAP> 
 === 7.5 === === 7.5 ===
-Unlike when we added the constraint file, at this point a //Define Module// dialog will pop up. You can rename your Verilog module using the //Module name// field, but this is unnecessary. We need to define the Verilog module's clock and led ports. You can click the //Add// ({{:vivado:getting_started:v2016.4:sources:add-port.png?direct|}}) button to add a port to the //I/O Port Definitions// list.+Unlike when the constraint file was added, at this point a //Define Module// dialog will pop up. You can rename your Verilog module using the //Module name// field, but this is unnecessary. The Verilog module's clock and led ports need to be defined. Clicking the //Add// ({{:vivado:getting_started:v2016.4:sources:add-port.png?direct|}}) button will add an empty slot for a port to the //I/O Port Definitions// list. 
 + 
 +{{ :vivado:getting_started:v2016.4:sources:define-module-clk.png?direct&500 |}}
  
 There are five fields to define for each of the module's I/O ports: There are five fields to define for each of the module's I/O ports:
-  * //Port Name// +  * **Port Name:** This field defines the name of the port and needs to match one of the names you used in your XDC file. 
-    * This field defines the name of the port and needs to match one of the names you used in your XDC file. +  * **Direction:** This drop-down menu can be set to //input//, //output//, or //inout//, defining the direction that signals propagate through this port, with respect to your module. Outputs are the signals that your module will be controlling. 
-  * //Direction// +  * **Bus:** This can be checked or not, when checked, this port consists of multiple single bit signals, grouped into a single bus. 
-    * This drop-down menu can be set to //input//, //output//, or //inout//, defining the direction that signals propagate through this port, with respect to your module. Outputs are the signals that your module will be controlling. +  * **MSB:** The index of the most significant bit of the port, if it is a bus. This option is grayed out for single-bit ports. 
-  * //Bus// +  * **LSB:** The index of the least significant bit of the port, if it is a bus. This option is grayed out for single-bit ports.
-    * This can be checked or not, when checked, this port consists of multiple single bit signals, grouped into a single bus. +
-  * //MSB// +
-    * The index of the most significant bit of the port, if it is a bus. This option is grayed out for single-bit ports. +
-  * //LSB// +
-    * The index of the least significant bit of the port, if it is a bus. This option is grayed out for single-bit ports.+
  
 <WRAP round center tip> <WRAP round center tip>
Line 389: Line 389:
 </WRAP> </WRAP>
  
-If your board uses differential clocking, add two single-bit input ports with the same names as the positive and negative clock signals we uncommented in your XDC file. Otherwise, add a single single-bit input port with the same name as the clock we uncommented in your XDC file.+If your board uses differential clocking, add two single-bit input ports with the same names as the positive and negative clock ports that were uncommented in your XDC file. Otherwise, add a single single-bit input port with the same name as the clock port that was uncommented in your XDC file.
  
-Add a single-bit output port with the same name as the LED port we uncommented in your XDC file.+Add a single-bit output port with the same name as the LED port that was uncommented in your XDC file.
  
 Once these two or three ports have been added, click //OK// to continue. Once these two or three ports have been added, click //OK// to continue.
-<WRAP column half> 
-{{ :vivado:getting_started:v2016.4:sources:define-module-clk.png?direct&500 |}} 
-</WRAP> 
-</WRAP> 
  
-<WRAP group> 
-<WRAP column half> 
-</WRAP> 
 === 7.6 === === 7.6 ===
-At this point, your new source file will be added to the //Design Sources// folder in the Sources pane of the Project Manager. Expand this folder and double click on your file to open it.+At this point, the new source file will be added to the //Design Sources// folder in the //Sources// pane of the //Project Manager//. Expand this folder and double click on the file to open it.
  
-We now need to write some Verilog code to define how the design will actually behave. +Next, some Verilog code needs to be written to define how the design will actually behave. 
-<WRAP column half> + 
-{{ :vivado:getting_started:v2016.4:sources:edit-source.png?direct&500 |}} +{{ :vivado:getting_started:v2016.4:sources:edit-source.png?direct&800 |}}
-</WRAP> +
-</WRAP>+
  
 Between the ');' that comes after the module's port list and the 'endmodule' statement, add the following code: Between the ');' that comes after the module's port list and the 'endmodule' statement, add the following code:
Line 421: Line 412:
 </code> </code>
  
-If your design is differentially clocked, add the following lines of code after ');' and before the 'reg [24:0] count = 0;' line:+If your board is differentially clocked, add the following lines of code after ');' and before the 'reg [24:0] count = 0;' line:
  
 <code verilog> <code verilog>
Line 433: Line 424:
 </code> </code>
  
-It should be noted that the rate at which the clock will blink will differ depending on the board used. System clocks on different Digilent boards run at a number of different rates, depending on the needs of the board. After completing this guide, the exercise of changing the provided code so that the clock blinks at 1 Hertz is suggested.+It should be noted that the rate at which the clock will blink will differ depending on the board used. System clocks on different Digilent boards run at a number of different rates, depending on the needs of the board. The system clock period in nanoseconds can be found on the //create_clock// line of the XDC file. 
 + 
 +After completing this guide, it is suggested to try changing the provided Verilog code so that the clock blinks at 1 Hertz - changing the XDC file beyond commenting or uncommenting entire lines is not recommended.
  
 ==== 8. Synthesis, Implementation, and Bitstream Generation ==== ==== 8. Synthesis, Implementation, and Bitstream Generation ====
Line 439: Line 432:
 In order to create a file that can be used to program the target board, each stage of the "compilation pipeline" needs to be run. In order to create a file that can be used to program the target board, each stage of the "compilation pipeline" needs to be run.
  
-This starts with Synthesis. Synthesis turns HDL files into a transistor level description based on timing and I/O constraints. To run Synthesis click either {{:vivado:getting_started:synth_ico.png?nolink}} in the toolbar or {{:vivado:getting_started:synth_btn.png?nolink}} in the Flow Navigator. The output of Synthesis is then passed to Implementation.+This starts with //Synthesis//. Synthesis turns HDL files into a transistor level description based on timing and I/O constraints. To run Synthesis click either {{:vivado:getting_started:synth_ico.png?nolink}} in the toolbar or {{:vivado:getting_started:synth_btn.png?nolink}} in the //Flow Navigator//. The output of Synthesis is then passed to Implementation.
  
-Implementation has several steps. The steps that are always run are Opt Design (Optimize the design to fit on the target FPGA), Place Design (Lay out the design in the target FPGA fabric), and Route Design (Route signals through the fabric). To run Implementation click either {{:vivado:getting_started:impl_ico.png?nolink}} in the toolbar or {{:vivado:getting_started:impl_btn.png?nolink}} in the Flow Navigator. This output is then passed on to the Bitstream Generator.+//Implementation// has several steps. The steps that are always run are //Opt Design// (Optimize the design to fit on the target FPGA), //Place Design// (Lay out the design in the target FPGA fabric), and //Route Design// (Route signals through the fabric). To run Implementation click either {{:vivado:getting_started:impl_ico.png?nolink}} in the toolbar or {{:vivado:getting_started:impl_btn.png?nolink}} in the //Flow Navigator//. This output is then passed on to the Bitstream Generator.
  
-The Bitstream Generator generates the final outputs needed for programming the FPGA. To run Bitstream Generation click either {{:vivado:getting_started:gen_bit_ico.png?nolink}} in the toolbar or {{:vivado:getting_started:gen_bit_btn.png?nolink}} in the Flow Navigator. With no settings changed, the generator will create a '.bit' file.+The //Bitstream Generator// generates the final outputs needed for programming the FPGA. To run Bitstream Generation click either {{:vivado:getting_started:gen_bit_ico.png?nolink}} in the toolbar or {{:vivado:getting_started:gen_bit_btn.png?nolink}} in the //Flow Navigator//. With no settings changed, the generator will create a '.bit' file.
  
 ==== 9. The Hardware Manager ==== ==== 9. The Hardware Manager ====
  
-The Hardware Manager is used for programming the target device.+The //Hardware Manager// is used for programming the target device.
  
 {{ :vivado:getting_started:v2016.4:hardware-manager:hardware-manager.png?direct&700 |}} {{ :vivado:getting_started:v2016.4:hardware-manager:hardware-manager.png?direct&700 |}}
Line 457: Line 450:
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-The first method is to manually open the target. This is required if the hardware is connected to another computer. To get to the Open Hardware Target wizard either open the Hardware Manager and click the {{:vivado:getting_started:open_target_banner.png?nolink}} link in the green banner or click the {{:vivado:getting_started:open_target_btn.png?nolink}} button in the Flow Navigator under {{:vivado:getting_started:hw_man_btn.png?nolink}}. From the drop-down that opens, select {{:vivado:getting_started:open_new_target_btn.png?nolink}}.+The first method is to manually open the target. This is required if the hardware is connected to another computer. To get to the //Open Hardware Target// wizard either open the //Hardware Manager// and click the {{:vivado:getting_started:open_target_banner.png?nolink}} link in the green banner or click the {{:vivado:getting_started:open_target_btn.png?nolink}} button in the //Flow Navigator// under {{:vivado:getting_started:hw_man_btn.png?nolink}}. From the drop-down that opens, select {{:vivado:getting_started:open_new_target_btn.png?nolink}}.
  
 Once the wizard opens, click //Next//. Once the wizard opens, click //Next//.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
-FIXME 
 {{ :vivado:getting_started:open_target.png?direct&500 |}} {{ :vivado:getting_started:open_target.png?direct&500 |}}
 </WRAP> </WRAP>
Line 469: Line 461:
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-The next screen asks if the hardware server is local or remote. If the board is connected to the host computer choose local, if it is connected to another machine choose remote and fill in the //Host Name// and //Port// fields appropriately.\+The next screen asks if the hardware server is local or remote. If the board is connected to the host computer choose local, if it is connected to another machine choose remote and fill in the //Host Name// and //Port// fields.
  
 Click //Next// to continue. Click //Next// to continue.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
-FIXME 
 {{ :vivado:getting_started:open_target_hw_srvr_settings.png?direct&500 |}} {{ :vivado:getting_started:open_target_hw_srvr_settings.png?direct&500 |}}
 </WRAP> </WRAP>
Line 501: Line 492:
 **2. Auto-Connect** **2. Auto-Connect**
  
-The second method is to automatically open the target. To get to the {{:vivado:getting_started:auto_connect_btn.png?nolink}} button either open the Hardware Manager and click the {{:vivado:getting_started:open_target_banner.png?nolink}} link in the green banner or click the {{:vivado:getting_started:open_target_btn.png?nolink}} button in the Flow Navigator under {{:vivado:getting_started:hw_man_btn.png?nolink}}. From the dropdown that opens select {{:vivado:getting_started:auto_connect_btn.png?nolink}}. Vivado will attempt to find a hardware server running on the local machine and will connect to the device on the server.+The second method is to automatically open the target. To get to the {{:vivado:getting_started:auto_connect_btn.png?nolink}} button either open the Hardware Manager and click the {{:vivado:getting_started:open_target_banner.png?nolink}} link in the //green banner// at the top of the window or click the {{:vivado:getting_started:open_target_btn.png?nolink}} button in the //Flow Navigator// under {{:vivado:getting_started:hw_man_btn.png?nolink}}. From the drop-down that opens select {{:vivado:getting_started:auto_connect_btn.png?nolink}}. Vivado will attempt to find a hardware server running on the local machine and will connect to the device on the server.
  
 ---- ----
Line 507: Line 498:
 **Programming** **Programming**
  
-To program the device with the bit file generated earlier, either click the {{:vivado:getting_started:prog_dev_banner.png?nolink}} link in the green banner or click the {{:vivado:getting_started:prog_dev_btn.png?nolink}} button in the Flow Navigator under {{:vivado:getting_started:hw_man_btn.png?nolink}}. From the drop-down that opens, select the device to program (Example: {{:vivado:getting_started:prog_dev_ex.png?nolink}}) and the following window will open:+To program the device with the bit file generated earlier, either click the {{:vivado:getting_started:prog_dev_banner.png?nolink}} link in the //green banner// at the top of the window or click the {{:vivado:getting_started:prog_dev_btn.png?nolink}} button in the //Flow Navigator// under {{:vivado:getting_started:hw_man_btn.png?nolink}}. From the drop-down that opens, select the device to program (Example: {{:vivado:getting_started:prog_dev_ex.png?nolink}}) and the following window will open:
  
 {{ :vivado:getting_started:v2016.4:project-manager:program-device.png?direct&500 |}} {{ :vivado:getting_started:v2016.4:project-manager:program-device.png?direct&500 |}}
  
-The //Bitstream File// field should be filled in with the bit file generated earlier. If not, click the {{:vivado:getting_started:browse_btn.png?nolink}} button at the right end of the field and navigate to \\ //<Project Directory>/<Project Name>.runs/impl_1/// and select the bit file (Example: {{:vivado:getting_started:bit_file_ex.png?nolink}}). Now click //Program//. This will connect to the board, clear the current configuration, and program using the new bit file.+The //Bitstream File// field should be automatically filled in with the bit file generated earlier. If not, click the {{:vivado:getting_started:browse_btn.png?nolink}} button at the right end of the field and navigate to \\ //<Project Directory>/<Project Name>.runs/impl_1/// and select the bit file (Example: {{:vivado:getting_started:bit_file_ex.png?nolink}}). Now click //Program//. This will connect to the board, clear the current configuration, and program using the new bit file.
  
 ----- -----
 +
 +==== 10. Finished! ====
  
 You should now see one of the LEDs on your board blinking! You should now see one of the LEDs on your board blinking!
  
-Be sure to visit your board's resource center for more tutorials and demo projects. A link to each resource center can be found [[https://reference.digilentinc.com/reference/programmable-logic/start|here]].+Be sure to visit your board's resource center for more tutorials and demo projects. A link to each resource center can be found [[/programmable-logic/start|here]].
  
-{{tag>learn programmable-logic software tutorial vivado arty-s7}}+{{tag>learn programmable-logic software tutorial vivado arty arty-a7 arty-s7 arty-z7 basys-3 cmod-a7 cmod-s7 cora-z7 genesys-2 nexys-4-ddr nexys-a7 nexys-video zybo-z7 zybo zedboard sword legacy}}