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vivado:getting_started:start [2016/09/06 19:17] – James Colvinvivado:getting_started:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 ----- -----
  
-===== Prerequisites ===== 
-Prior to starting this guide make sure to install Vivado. For more information see our [[learn:software:tutorials:vivado-install-guide:|Installing Vivado]] guide. 
 ===== Introduction ===== ===== Introduction =====
  
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 The goal of this guide is to familiarize the reader with the Vivado tools through the hello world of hardware, blinking an LED. The goal of this guide is to familiarize the reader with the Vivado tools through the hello world of hardware, blinking an LED.
  
-This guide was created using Vivado 2016.2. +**Note:** //While this guide was created using Vivado 2016.4, the workflow described has not substantially changed, and the guide works as described through Vivado 2019.2, the latest version as of time of writing.// 
-==== 1. Starting Vivado ====+ 
 +---- 
 +===== Prerequisites ===== 
 +Prior to starting this guide make sure to install Vivado: 
 +  * For versions 2019.2 and later, see [[vivado:installing-vivado:v2019.2]]. 
 +  * For versions prior to 2019.2, see [[vivado:installing-vivado:start]]. 
 + 
 +---- 
 +===== Guide ===== 
 +==== 1. Launching Vivado ====
 <WRAP group> <WRAP group>
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 **Windows**\\ **Windows**\\
-Open the start menu and go to //All Programs->Xilinx Design Tools->Vivado <version>->Vivado <version>//+Open the start menu or desktop shortcut created during the installation process.
 </WRAP> </WRAP>
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-{{ :vivado:getting_started:windows_start_vivado.png?direct&500 |}}+{{ :vivado:getting_started:v2016.4:vivado-shortcut.png?direct&500 |}}
 </WRAP> </WRAP>
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 **Linux**\\ **Linux**\\
-Open a Terminal and run+Open a terminal, cd into a working directory that can be cluttered with temporary Vivado files and logs, then run the following:
 <code>source <install_path>/Vivado/<version>/settings64.sh && vivado</code> <code>source <install_path>/Vivado/<version>/settings64.sh && vivado</code>
 </WRAP> </WRAP>
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 This is the screen that displays after Vivado starts up. The buttons are described below using the image as a guide. This is the screen that displays after Vivado starts up. The buttons are described below using the image as a guide.
  
-{{ :vivado:getting_started:vivado_home_outlined.png?direct&500 |}}+{{ :vivado:getting_started:v2016.4:vivado-home-outline.jpg?direct&800 |}}
  
 == 1. Create New Project == == 1. Create New Project ==
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 == 2. Open Project == == 2. Open Project ==
  
-This button will open a file browser. Navigate to the desired XPR file and click //Open// to open the project in Vivado.+This button will open a file browser. Navigate to the desired Xilinx Project (.xpr) file and click //Open// to open the project in Vivado.
  
 == 3. Open Example Project == == 3. Open Example Project ==
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 == 4. Open Hardware Manager == == 4. Open Hardware Manager ==
  
-This will open the Hardware Manager without an associated project. If connecting to and programming a device is all that is required by the user this is the button to use.+This will open the Hardware Manager without an associated project. If connecting to and programming a device is all that is required by the user, then this is the button to use. 
 ==== 3. Creating a New Project ==== ==== 3. Creating a New Project ====
  
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-{{ :vivado:getting_started:create_new_project_button.png?direct&500 |}}+{{ :vivado:getting_started:v2016.4:vivado-home-create-new.jpg?direct&500 |}}
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 === 3.2 === === 3.2 ===
-The text in the dialog describes the steps that will be taken to create a project. Click //Next// to continue to the first step.+The text in this dialog describes the steps that will be taken to create a project. Click //Next// to continue to the first step.
 </WRAP> </WRAP>
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-{{ :vivado:getting_started:new_project.png?direct&500 |}}+{{ :vivado:getting_started:v2016.4:new-project-wiz-0.png?direct&500 |}}
 </WRAP> </WRAP>
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 === 3.3 === === 3.3 ===
 The first step is to set the name of the project. Vivado will use this name when generating its folder structure. The first step is to set the name of the project. Vivado will use this name when generating its folder structure.
- 
 <WRAP center round important> <WRAP center round important>
-Important: Do NOT use spaces in your project name or location path. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]].+=== Important === 
 +Do NOT use spaces in your project name or location path. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]].
 </WRAP> </WRAP>
 +Click //Next// to continue.
 </WRAP> </WRAP>
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-{{ :vivado:getting_started:project_name.png?direct&500 |}}+{{ :vivado:getting_started:v2016.4:new-project-wiz-1.png?direct&500 |}}
 </WRAP> </WRAP>
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 === 3.4 === === 3.4 ===
-Now that the project has a name and a place to save important files we need to create the necessary source files. To add a Verilog or VHDL file click the create file button.+Now that the project has a name and a place to save its files we need to select the type of project we will be creating. Select //RTL Project// and make sure to check //Do not specify sources at this time//. Source files will be added and created after the project has been created. Advanced users may use the other options on this screen, but they will not be covered in this guide. 
 + 
 +Click //Next// to continue.
 </WRAP> </WRAP>
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-{{ :vivado:getting_started:add_sources.png?direct&500 |}}+{{ :vivado:getting_started:v2016.4:new-project-wiz-2.png?direct&500 |}}
 </WRAP> </WRAP>
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 === 3.5 === === 3.5 ===
-This will open the //Create Source File// dialog, shown below. This dialog has three options for the new file. The first is the type of file. This allows for selecting between different HDL file types, Verilog, VHDL, Verilog Header, and SystemVerilog. The final type available is the Memory File option. This is used for memory device initialization, most of the time this can be ignored. +<WRAP round center important> 
- +=== Important === 
-The second box is for the file name. Enter the name for the file to create. Including the file extension is optional, Vivado will add one based on the file type selected. The final option is where to store the file. Most of the time this can be left as //<Local to Project>//.+If your board does not appear in this list, then Digilent's board files haven't yet been installed. If this is the case, revisit the prerequisites section of this guide, then close Vivado and start again from the beginning. 
 +</WRAP> 
 +Now it is time to choose the target device. Click the //Boards// tab at the top of the dialog, then select your board from the list.
  
-<WRAP center round important> +Click //Next// to continue.
-Important: Do NOT use spaces in your file name. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]]. +
-</WRAP>+
 </WRAP> </WRAP>
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-{{ :vivado:getting_started:create_source_file.png?direct&500 |}}+{{ :vivado:getting_started:v2016.4:new-project-wiz-3.png?500 |}}
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-=== 3.6 === +=== 3.6 == 
-It is also possible to import source files into the project. In the //Add Sources// dialog click the //Add Files// button and navigate to the source file to import into the project. Unless there is reason not to, make sure that the //Copy sources into project// check box is checked to make a copy of the source file local to the project. Since the file is copied, any changes made to the file inside one project do not affect the original file.+The next section gives a summary of the options selected throughout the wizard. Verify that the information looks correct and click //Finish//.
 </WRAP> </WRAP>
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-{{ :vivado:getting_started:import_sources.png?direct&500 |}}+{{ :vivado:getting_started:v2016.4:new-project-wiz-4.png?500 |}}
 </WRAP> </WRAP>
 </WRAP> </WRAP>
  
 +
 +==== 4. The Flow Navigator ====
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-=== 3.7 === +The //Flow Navigator// is the most important pane of the main Vivado window to know. It is how a user navigates between different Vivado tools. 
-After adding the HDL files and clicking //Next// in the main dialog, the next dialog is displayed. This dialog is for adding IP to the project. This is used in more advanced designs and is outside the scope of this guide. Click //Next//.+ 
 +The Navigator is broken into seven sections: 
 +  * //Project Manager// 
 +    * Allows for quick access to project settings, adding sources, language templates, and the IP catalog 
 +  * //IP Integrator// 
 +    * Tools for creating Block Designs 
 +  * //Simulation// 
 +    * Allows a developer to verify the output of their design prior to programming their device 
 +  * //RTL Analysis// 
 +    * lets the developer see how the tools are interpreting their code 
 +  * //Synthesis// 
 +    * Gives access to Synthesis settings and post-synthesis reports 
 +  * //Implementation// 
 +    * Gives access to Implementation settings and post-implementation reports 
 +  * //Program and Debug// 
 +    * Access to settings for bitstream generation and the Hardware Manager
 </WRAP> </WRAP>
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-{{ :vivado:getting_started:add_existing_ip.png?direct&500 |}}+{{ vivado:getting_started:flownav.png?direct&200 |}}
 </WRAP> </WRAP>
 </WRAP> </WRAP>
 +
 +==== 5. The Project Manager ====
  
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-=== 3.8 === +This tool is where most development will occur and is the initial tool open after creating a new project.
-The next section is for adding a constraints file. Constraints files control how signals are routed, define clocks, and define timing constraints. Click the //Create File// button to open the //Create Constraints File// dialog.+
 </WRAP> </WRAP>
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-{{ :vivado:getting_started:add_constraints.png?direct&500 |}}+{{ :vivado:getting_started:v2016.4:project-manager:project-manager.png?direct&600 |}}
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-=== 3.9 === +The //Project Manager// consists of four panes, //Sources//, //Properties//, //Results//, and the //Workspace//.
-Again the dialog presents three options. the file name and file location have the same properties as the ones in the //Create Source File// dialog. What is different is the file types that can be created. The only option available is XDC which stands for Xilinx Design Constraints. This file will define clocking, pin mapping, and timing restrictions. +
- +
-<WRAP center round important> +
-Important: Do NOT use spaces in your file name. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]]. +
-</WRAP>+
 </WRAP> </WRAP>
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-{{ :vivado:getting_started:create_constraints_file.png?direct&500 |}}+{{ :vivado:getting_started:v2016.4:project-manager:project-manager-explained.png?direct&600 |}}
 </WRAP> </WRAP>
 </WRAP> </WRAP>
  
 +<WRAP group>
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-=== 3.10 === +The //Sources// pane contains the project hierarchy and is used for opening up files. The folder structure is organized such that the HDL files are kept under the //Design Sources// folder, constraints are kept under the //Constraints// folder, and simulation files are kept under the //Simulation Sources// folder. Files can be opened in the Workspace by double-clicking on the corresponding entry in the Sources pane. Sources can also be added by either right clicking the folder to add the file to and selecting //Add Sources// or by clicking the //Add Sources// button ({{:vivado:getting_started:add_sources_btn.png?nolink}}). 
-Now that the necessary files have been created it is time to choose the target device. There are two ways to choose a target. The first is from the actual on board component and the second is from installing the appropriate board files and picking a board.+</WRAP> 
 +<WRAP column half> 
 +{{ :vivado:getting_started:v2016.4:project-manager:sources-pane.png?direct&500 |}} 
 +</WRAP>
 </WRAP> </WRAP>
  
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-== 3.10.1 == +The //Properties// pane allows for viewing and editing of file properties. When a file is selected in the Sources pane its properties are shown in here. This pane can usually be ignored.
-To pick a target from the on board component find the part number for the IC and find it in the selection list. There are two places to find a part number for our boards. The first is to look at the actual component on the board and try to discern the writing. The other is to look on the [[reference:programmable-logic:|reference page]] for the target board.+
 </WRAP> </WRAP>
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-{{ :vivado:getting_started:default_part_-_parts.png?direct&500 |}}+{{ :vivado:getting_started:v2016.4:project-manager:properties-pane.png?direct&500 |}}
 </WRAP> </WRAP>
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-== 3.10.2 == +The unnamed pane at the bottom of the Project Manager window consists of several different useful tools for debugging a project. The most important one to know is the //Messages// tool. This tool parses the Tcl console for errors, warnings, and other important information and displays it in an informative way. 
-To pick a target from the boards list, install the [[reference:software:vivado:board-files#installation|board files]] prior to creating a new project. Then select the board to use as a target from the list.+ 
 +These tools can be accessed by selecting the different tabs at the bottom of this pane.
 </WRAP> </WRAP>
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-{{ :vivado:getting_started:default_part_-_boards.png?direct&500 |}}+{{ :vivado:getting_started:v2016.4:project-manager:results-pane.png?direct&700 |}}
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-=== 3.11 == +The //Tcl Console// is a tool that allows for running commands directly without the use of the main user interface. Some messages may link to the Tcl Console to provide more information regarding an error.
-The next section gives a summary of the options selected throughout the wizard. Verify that the information looks correct and click //Finish//.+
 </WRAP> </WRAP>
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-{{ :vivado:getting_started:new_project_summary.png?direct&500 |}}+{{ :vivado:getting_started:v2016.4:project-manager:tcl-console-tab.png?direct&700 |}}
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-=== 3.12 === +The //Reports// tool is useful for quickly jumping to any one of the many reports that Vivado generates on a design. These reports include power, timing, and utilization just to name a few.
-Since new source files were created, Vivado will now show a new dialog box for defining a module for each new source file that it was told to create. Here the inputs and outputs of a module can be defined. +
- +
-Each section can be interpreted as follows: +
- +
- +
-^ Field      ^ Description                                      ^ Example    ^ +
-^ Port Name  | The name to give the new port                    | //leds//   | +
-^ Direction  | Is the port an input, output, or bi-directional  | //output// | +
-^ Bus        | Is the port a bus/multiple bits?                 | //x//      | +
-^ MSB        | What is the Most Significant Bit?                | //7//      | +
-^ LSB        | What is the Least Significant Bit?               | //0//      | +
- +
-Fill out the port definitions for clk and led as shown then click //OK//.+
 </WRAP> </WRAP>
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- {{ :vivado:getting_started:define_module.png?direct&500 |}}+{{ :vivado:getting_started:v2016.4:project-manager:reports-tab.png?direct&700 |}}
 </WRAP> </WRAP>
 </WRAP> </WRAP>
  
-==== 4. The Flow Navigator ==== 
 <WRAP group> <WRAP group>
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-The Flow Navigator is the most important pane to know. It is how a user navigates between different Vivado tools. +The //Log// displays the output from the latest Synthesis, Implementation, and Simulation runs. Digging into this is usually not necessary as the reports and messages view store the information in the log in a more readable format.
- +
-The Navigator is broken into seven sections: +
-  * Project Manager +
-    * Allows for quick access to project settings, adding sources, language templates, and the IP catalog +
-  * IP Integrator +
-    * Tools for creating Block Designs +
-  * Simulator +
-    * Allows a developer to verify the output prior to programming their device +
-  * RTL Analysis +
-    * lets the developer see how the tools are interpreting their code +
-  * Synthesis +
-    * Gives access to Synthesis settings and post-synthesis reports +
-  * Implementation +
-    * Gives access to Implementation settings and post-implementation reports +
-  * Program and Debug +
-    * Access to settings for bitstream generation and the Hardware Manager+
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
-{{ vivado:getting_started:flownav.png?direct&200 |}} +{{ :vivado:getting_started:v2016.4:project-manager:log-tab.png?direct&700 |}}
 </WRAP> </WRAP>
 </WRAP> </WRAP>
-==== 5. The Project Manager ==== 
  
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-This tool is where most development will occur and is the initial tool open after creating a new project.+The last tool is the //Design Runs//. Using this tool run settings can be edited and new runs can be created. This tool is useful when targeting multiple devices with the same design.
 </WRAP> </WRAP>
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-{{ :vivado:getting_started:proj_man.png?direct&600 |}} +{{ :vivado:getting_started:v2016.4:project-manager:design-runs-tab.png?direct&700 |}}
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-The Project Manager consists of four panes, Sources, Properties, Results, and the Workspace.+The most important pane in the Project Manager is the //Workspace//. The Workspace is where reports are opened for viewing and HDL/constraints files are opened for editing. Initially the Workspace displays the //Project Summary// which show some basic information from some of the reports.
 </WRAP> </WRAP>
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-{{ :vivado:getting_started:proj_man_outlined.png?direct&600 |}}+{{ :vivado:getting_started:v2016.4:project-manager:workspace-pane.png?direct&500 |}}
 </WRAP> </WRAP>
 </WRAP> </WRAP>
 +
 +==== 6. Adding a Constraint File ====
 +
 +In order to connect HDL code with the physical pins of the FPGA, a constraint file needs to be added or created. Digilent has produced a Xilinx Design Constraint (XDC) file for each of our boards. Download [[https://github.com/Digilent/digilent-xdc/archive/master.zip|digilent-xdc-master.zip]], the ZIP Archive containing each of these master XDC files, then extract it in a location you will remember.
  
 <WRAP group> <WRAP group>
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-The Sources pane contains the project hierarchy and is used for opening up files. The folder structure is organized such that the HDL files are kept under the //Design Sources// folder, constraints are kept under the //Constraints// folder, and simulation files are kept under the //Simulation Sources// folder. Files can be opened in the Workspace by double-clicking on the corresponding entry in the Sources pane. Sources can also be added by either right clicking the folder to add the file to and selecting //Add Sources// or by clicking the //Add Sources// button ({{:vivado:getting_started:add_sources_btn.png?nolink}}).+=== 6.1 === 
 +In the //Project Manager// section of the //Flow Navigator//, click the {{:vivado:getting_started:v2016.4:sources:add-sources.png}} button. In the wizard that pops up, select //Add or create constraints// then click //Next//.
 </WRAP> </WRAP>
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-{{ :vivado:getting_started:proj_man_sources_pane.png?direct&500 |}}+{{ :vivado:getting_started:v2016.4:sources:add-constr-1.png?direct&500 |}}
 </WRAP> </WRAP>
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-The Properties pane allows for viewing and editing of file properties. When a file is selected in the Sources pane its properties are shown in here. This pane can usually be ignored.+=== 6.2 === 
 +At this stage, Vivado provides a list of all of the constraint files that will be added or created when we click Finish. Currently this list is empty, this will change when files have been added or created. A constraint file will not be created from scratch in this guide, so click //Add Files//.
 </WRAP> </WRAP>
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-{{ :vivado:getting_started:proj_man_props_pane.png?direct&500 |}}+{{ :vivado:getting_started:v2016.4:sources:add-constr-2.png?direct&500 |}}
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-The Results pane consists of several different useful tools for debugging a project. The most important one to know is the Messages tool. This tool parses the Tcl console for errors, warnings, and other important information and displays it in an informative way.+=== 6.3 === 
 +Find the directory you extracted the //digilent-xdc-master.zip// archive into, then click on the file for your board. This should add the name of the file to the //File Name// field. 
 + 
 +Click //OK// to continue.
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-{{ :vivado:getting_started:proj_man_results_msgs.png?direct&700 |}}+{{ :vivado:getting_started:v2016.4:sources:add-constr-3.png?direct&500 |}}
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-The Tcl console is a tool that allows for running commands directly without the use of the main user interface. Some messages may direct to the Tcl console for more information regarding an error.+=== 6.4 === 
 +Make sure that the selected XDC file has been added into the list of sources, and that the //Copy constraint files into project// is checked, then click //Finish//. 
 + 
 +**Note:** //Leaving the Copy... box unchecked means that any editing done to the constraint file will be reflected in the original copy. Checking the box is highly recommended//
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-{{ :vivado:getting_started:proj_man_results_tcl_con.png?direct&700 |}}+{{ :vivado:getting_started:v2016.4:sources:add-constr-4.png?direct&500 |}}
 </WRAP> </WRAP>
 </WRAP> </WRAP>
 +=== 6.5 ===
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-The Reports tool is useful for quickly jumping to any one of the many reports that Vivado generates on a design. These reports include power, timing, and utilization just to name a few.+In the //Sources// pane of the //Project Manager//, expand the //Constraints// folder, then double click on the XDC file you just added. Each of Digilent's XDC files contains constraints for each of the commonly used peripherals on their respective boards. For this demo, constraining the default system clock and a single led is required. 
 + 
 +Find and uncomment the lines that call //get_ports// on the names led[0] and clk by removing the '#' symbol at the beginning of the line. On some boards the clock port will consist of two different ports, clk_p and clk_n. The clock port is occasionally named something like sysclk, but should appear at the top of the XDC file. Uncomment the //create_clock// line that follows the clock port/s definition as well. 
 +<WRAP round center tip> 
 +=== Tip === 
 +A board using clk_p/clk_n pins means that the input clock that uses differential logic. If you want to know more read this article on [[wp>low-voltage differential signalling]]. 
 +</WRAP> 
 +Change the name inside of the get_ports call to 'led' from 'led[0]'. Do the same for the clock if it is something other than 'clk' or 'clk_p' and 'clk_n'.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
-{{ :vivado:getting_started:proj_man_results_reports.png?direct&700 |}}+{{ :vivado:getting_started:v2016.4:edit-constraints.png?direct&500 |}}
 </WRAP> </WRAP>
 </WRAP> </WRAP>
 +
 +==== 7. Creating a Verilog Source File ====
  
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-The Log displays the output from the latest Synthesis, Implementation, and Simulation runs. Digging into this is not necessary as the reports and messages view store the information in the log in a more readable format.+=== 7.1 === 
 +In the //Project Manager// section of the //Flow Navigator//, click the {{:vivado:getting_started:v2016.4:sources:add-sources.png}} button again. Select //Add or create design sources// then click //Next//.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
-{{ :vivado:getting_started:proj_man_results_log.png?direct&700 |}}+{{ :vivado:getting_started:v2016.4:sources:create-source-1.png?direct&500 |}}
 </WRAP> </WRAP>
 </WRAP> </WRAP>
Line 319: Line 335:
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-The last tool is the Design Runs. Using this tool run settings can be edited and new runs can be created. This tool is useful when targeting multiple devices with the same design.+=== 7.2 === 
 +As before, at this stage, we will be provided a list of all of the source files that will be added or created when we click Finish. Instead of clicking Add Files, click //Create File//. 
 +<WRAP round center tip> 
 +=== Tip === 
 +It is also possible to add existing source files in the same way as we added the constraint file above. 
 +</WRAP>
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
-{{ :vivado:getting_started:proj_man_results_runs.png?direct&700 |}}+{{ :vivado:getting_started:v2016.4:sources:create-source-2.png?direct&500 |}}
 </WRAP> </WRAP>
 </WRAP> </WRAP>
Line 328: Line 349:
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-The most important pane in the Project Manager is the Workspace. The Workspace is where reports are opened for viewing and HDL/constraints files are opened for editing. Initially the Workspace displays the Project Summary which show some basic information from some of the reports.+=== 7.3 === 
 +You will be prompted to select a //File type//, //File name//, and //File location//. Make sure to pick //Verilog// and //<Local to project>// for the type and location. Give your file a name ending in '.v'. 
 +<WRAP center round important> 
 +=== Important === 
 +Do NOT use spaces in your file name. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]]. 
 +</WRAP> 
 +Click //OK// to continue.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
-{{ :vivado:getting_started:proj_man_ws.png?direct&500 |}}+{{ :vivado:getting_started:v2016.4:sources:create-source-3.png?direct&500 |}}
 </WRAP> </WRAP>
 </WRAP> </WRAP>
-==== 6. Writing HDL and Constraints ==== 
  
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-To actually get the board to blink an LED, code needs to be written in both the Verilog and the constraints files. Opening up the Verilog file (top.v in this guide) this window should open in the workspace area.+=== 7.4 === 
 +Make sure that the new Verilog source file has been added into the list of sources, then click //Finish//.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
-{{ :vivado:getting_started:src_init.png?direct&500 |}}+{{ :vivado:getting_started:v2016.4:sources:create-source-4.png?direct&500 |}}
 </WRAP> </WRAP>
 </WRAP> </WRAP>
  
-Between lines 26 and 27 add the following code:+=== 7.5 === 
 +Unlike when the constraint file was added, at this point a //Define Module// dialog will pop up. You can rename your Verilog module using the //Module name// field, but this is unnecessary. The Verilog module's clock and led ports need to be defined. Clicking the //Add// ({{:vivado:getting_started:v2016.4:sources:add-port.png?direct|}}) button will add an empty slot for a port to the //I/O Port Definitions// list. 
 + 
 +{{ :vivado:getting_started:v2016.4:sources:define-module-clk.png?direct&500 |}} 
 + 
 +There are five fields to define for each of the module's I/O ports: 
 +  * **Port Name:** This field defines the name of the port and needs to match one of the names you used in your XDC file. 
 +  * **Direction:** This drop-down menu can be set to //input//, //output//, or //inout//, defining the direction that signals propagate through this port, with respect to your module. Outputs are the signals that your module will be controlling. 
 +  * **Bus:** This can be checked or not, when checked, this port consists of multiple single bit signals, grouped into a single bus. 
 +  * **MSB:** The index of the most significant bit of the port, if it is a bus. This option is grayed out for single-bit ports. 
 +  * **LSB:** The index of the least significant bit of the port, if it is a bus. This option is grayed out for single-bit ports. 
 + 
 +<WRAP round center tip> 
 +=== Tip === 
 +If you are defining a module which will be instantiated in another module, which we will not go into in this guide, be aware that the port names should not be declared in the XDC, this is only done for your 'top' module. 
 +</WRAP> 
 + 
 +If your board uses differential clocking, add two single-bit input ports with the same names as the positive and negative clock ports that were uncommented in your XDC file. Otherwise, add a single single-bit input port with the same name as the clock port that was uncommented in your XDC file. 
 + 
 +Add a single-bit output port with the same name as the LED port that was uncommented in your XDC file. 
 + 
 +Once these two or three ports have been added, click //OK// to continue. 
 + 
 +=== 7.6 === 
 +At this point, the new source file will be added to the //Design Sources// folder in the //Sources// pane of the //Project Manager//. Expand this folder and double click on the file to open it. 
 + 
 +Next, some Verilog code needs to be written to define how the design will actually behave. 
 + 
 +{{ :vivado:getting_started:v2016.4:sources:edit-source.png?direct&800 |}} 
 + 
 +Between the ');' that comes after the module's port list and the 'endmodule' statement, add the following code:
  
 <code verilog> <code verilog>
Line 355: Line 412:
 </code> </code>
  
-If the Genesys 2, NetFPGA-1G-CML, or NetFPGA-SUME is being targeted, clear the contents of the whole file and replace it with the following:+If your board is differentially clocked, add the following lines of code after ');' and before the 'reg [24:0] count = 0;' line:
  
 <code verilog> <code verilog>
-module top( +wire clk;
-    input clk_p, +
-    input clk_n, +
-    output led +
-    ); +
-     +
-    wire clk; +
-     +
-    IBUFGDS #( +
-     +
-    ) clk_inst ( +
-        .O(clk), +
-        .I(clk_p), +
-        .IB(clk_n) +
-    ); +
-     +
-    reg [25:0] count = 0;+
  
-    assign led = count[25]; +IBUFGDS clk_inst ( 
- +    .O(clk), 
-    always @ (posedge(clk)) count <= count + 1; +    .I(clk_p), 
- +    .IB(clk_n) 
-endmodule+);
 </code> </code>
  
-This is different because those boards have a input clock that uses differential logic. If you want to know more read this article on [[wp>low-voltage differential signalling]]. +It should be noted that the rate at which the clock will blink will differ depending on the board used. System clocks on different Digilent boards run at a number of different rates, depending on the needs of the board. The system clock period in nanoseconds can be found on the //create_clock// line of the XDC file.
- +
-<WRAP group> +
-<WRAP column half> +
-Once added the source file will look like this: +
-</WRAP> +
-<WRAP column half> +
-{{ :vivado:getting_started:src_final.png?direct&500 |}} +
-</WRAP> +
-</WRAP> +
- +
-Now open the XDC file. At the moment it is empty so paste in the code below depending on the target board. +
- +
-^  Constraint File Source Code                     || +
-^ Board                         ^ Constraint Code   ^ +
-| Arty                          | <code> +
-set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports clk] +
-    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] +
-set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS33 } [get_ports led] +
-</code>                                             | +
-| Basys 3                       | <code> +
-set_property -dict { PACKAGE_PIN W5   IOSTANDARD LVCMOS33 } [get_ports clk] +
-    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] +
-set_property -dict { PACKAGE_PIN U16  IOSTANDARD LVCMOS33 } [get_ports led] +
-</code>                                             | +
-| CmodA7                        | <code> +
-set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports clk] +
-    create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports clk] +
-set_property -dict { PACKAGE_PIN A17   IOSTANDARD LVCMOS33 } [get_ports led] +
-</code>                                             | +
-| Genesys 2                     | <code> +
-set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVDS} [get_ports clk_n] +
-set_property -dict {PACKAGE_PIN AD12 IOSTANDARD LVDS} [get_ports clk_p] +
-    create_clock -period 5.000 -name sys_clk_pin -waveform {0.000 2.500} -add [get_ports clk_p] +
-set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS33} [get_ports led] +
-</code>                                             | +
-| Nexys 4                       | <code> +
-set_property -dict { PACKAGE_PIN E3   IOSTANDARD LVCMOS33 } [get_ports clk] +
-    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] +
-set_property -dict { PACKAGE_PIN T8   IOSTANDARD LVCMOS33 } [get_ports led] +
-</code>                                             | +
-| Nexys 4 DDR                   | <code> +
-set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports clk] +
-    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] +
-set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports led] +
-</code>                                             | +
-| Nexys Video                   | <code> +
-set_property -dict { PACKAGE_PIN R4    IOSTANDARD LVCMOS33 } [get_ports clk] +
-    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] +
-set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS25 } [get_ports led] +
-</code>                                             | +
-| NetFPGA-1G-CML                | <code> +
-set_property -dict { PACKAGE_PIN AA2   IOSTANDARD LVDS     } [get_ports clk_n] +
-set_property -dict { PACKAGE_PIN AA3   IOSTANDARD LVDS     } [get_ports clk_p] +
-    create_clock -add -name sys_clk_pin -period 5.00 -waveform {0 2.5} [get_ports clk_n] +
-set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports led] +
-</code>                                             | +
-| NetFPGA-SUME                  | <code> +
-set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVDS     } [get_ports clk_n] +
-set_property -dict { PACKAGE_PIN H19   IOSTANDARD LVDS     } [get_ports clk_p] +
-    create_clock -add -name sys_clk_pin -period 5.00 -waveform {0 2.5} [get_ports clk_n] +
-set_property -dict { PACKAGE_PIN AR22  IOSTANDARD LVCMOS15 } [get_ports led] +
-</code>                                             | +
-| ZedBoard                      | <code> +
-set_property -dict { PACKAGE_PIN Y9    IOSTANDARD LVCMOS33 } [get_ports clk] +
-    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] +
-set_property -dict { PACKAGE_PIN T22   IOSTANDARD LVCMOS33 } [get_ports led] +
-</code>                                             | +
-| Zybo                          | <code> +
-set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports clk] +
-    create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports clk] +
-set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports led] +
-</code>                                             |+
  
-Once that is done the code is ready to be "compiled."+After completing this guide, it is suggested to try changing the provided Verilog code so that the clock blinks at 1 Hertz - changing the XDC file beyond commenting or uncommenting entire lines is not recommended.
  
 ==== 8. Synthesis, Implementation, and Bitstream Generation ==== ==== 8. Synthesis, Implementation, and Bitstream Generation ====
  
-In order to create a file that can be used to program the target the "compilation-pipeline" needs to be done.+In order to create a file that can be used to program the target board, each stage of the "compilation pipeline" needs to be run.
  
-This starts with Synthesis. Synthesis turns HDL files into a transistor level description based on timing and I/O constraints. To run Synthesis click either {{:vivado:getting_started:synth_ico.png?nolink}} in the toolbar or {{:vivado:getting_started:synth_btn.png?nolink}} in the Flow Navigator. The output of Synthesis is then passed to Implementation.+This starts with //Synthesis//. Synthesis turns HDL files into a transistor level description based on timing and I/O constraints. To run Synthesis click either {{:vivado:getting_started:synth_ico.png?nolink}} in the toolbar or {{:vivado:getting_started:synth_btn.png?nolink}} in the //Flow Navigator//. The output of Synthesis is then passed to Implementation.
  
-Implementation has several steps. The steps that are always run are Opt Design (Optimize the design to fit on the target FPGA), Place Design (Layout the design in the target FPGA fabric), and Route Design (Route signals through the fabric). To run Implementation click either {{:vivado:getting_started:impl_ico.png?nolink}} in the toolbar or {{:vivado:getting_started:impl_btn.png?nolink}} in the Flow Navigator. This output is then passed on to the Bitstream Generator.+//Implementation// has several steps. The steps that are always run are //Opt Design// (Optimize the design to fit on the target FPGA), //Place Design// (Lay out the design in the target FPGA fabric), and //Route Design// (Route signals through the fabric). To run Implementation click either {{:vivado:getting_started:impl_ico.png?nolink}} in the toolbar or {{:vivado:getting_started:impl_btn.png?nolink}} in the //Flow Navigator//. This output is then passed on to the Bitstream Generator.
  
-The Bitstream Generator generates the final outputs needed for programming the FPGA. To run Bitstream Generation click either {{:vivado:getting_started:gen_bit_ico.png?nolink}} in the toolbar or {{:vivado:getting_started:gen_bit_btn.png?nolink}} in the Flow Navigator. With no settings changed, the generator will create a BIT file.+The //Bitstream Generator// generates the final outputs needed for programming the FPGA. To run Bitstream Generation click either {{:vivado:getting_started:gen_bit_ico.png?nolink}} in the toolbar or {{:vivado:getting_started:gen_bit_btn.png?nolink}} in the //Flow Navigator//. With no settings changed, the generator will create a '.bit' file.
  
 ==== 9. The Hardware Manager ==== ==== 9. The Hardware Manager ====
  
-The Hardware Manager is used for programming the target device.+The //Hardware Manager// is used for programming the target device.
  
-{{ :vivado:getting_started:hard_man.png?direct&500 |}}+{{ :vivado:getting_started:v2016.4:hardware-manager:hardware-manager.png?direct&700 |}}
  
-The first step to programming a device is to connect to it. There are two ways to do this.+The first step to programming a device is to connect the Vivado Hardware Server to it. There are two ways to do this.
  
 **1. Open New Hardware Target** **1. Open New Hardware Target**
Line 481: Line 450:
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-The first method is to manually open the target. This is required if the hardware is connected to another computer. To get to the Open Hardware Target wizard either open the Hardware Manager and click the {{:vivado:getting_started:open_target_banner.png?nolink}} link in the green banner or click the {{:vivado:getting_started:open_target_btn.png?nolink}} button in the Flow Navigator under {{:vivado:getting_started:hw_man_btn.png?nolink}}. From the dropdown that opens select {{:vivado:getting_started:open_new_target_btn.png?nolink}}. The wizard will open, click //Next//.+The first method is to manually open the target. This is required if the hardware is connected to another computer. To get to the //Open Hardware Target// wizard either open the //Hardware Manager// and click the {{:vivado:getting_started:open_target_banner.png?nolink}} link in the green banner or click the {{:vivado:getting_started:open_target_btn.png?nolink}} button in the //Flow Navigator// under {{:vivado:getting_started:hw_man_btn.png?nolink}}. From the drop-down that opens, select {{:vivado:getting_started:open_new_target_btn.png?nolink}}. 
 + 
 +Once the wizard opens, click //Next//.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 490: Line 461:
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-The next screen asks if the hardware server is local or remote. If the board is connected to the host computer choose local, if it is connected to another machine choose remote and fill in the //Host Name// and //Port// fields appropriately. Click //Next//.+The next screen asks if the hardware server is local or remote. If the board is connected to the host computer choose local, if it is connected to another machine choose remote and fill in the //Host Name// and //Port// fields. 
 + 
 +Click //Next// to continue.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 499: Line 472:
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-This screen gives a list of devices connected to the hardware server. If there is only one connected it should be the only device shown. If there are multiple connected determine the serial number of the device to connect to and find it in the list. Click //Next//.+This screen gives a list of devices connected to the hardware server. If there is only one connected it should be the only device shown. If there are multiple connected devices, determine the serial number of the device to connect to and find it in the list. 
 + 
 +Click //Next// to continue.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
-{{ :vivado:getting_started:open_target_slct_hw_trgt.png?direct&500 |}}+{{ :vivado:getting_started:v2016.4:project-manager:open-new-hardware-target.png?direct&500 |}}
 </WRAP> </WRAP>
 </WRAP> </WRAP>
Line 517: Line 492:
 **2. Auto-Connect** **2. Auto-Connect**
  
-The second method is to automatically open the target. To get to the {{:vivado:getting_started:auto_connect_btn.png?nolink}} button either open the Hardware Manager and click the {{:vivado:getting_started:open_target_banner.png?nolink}} link in the green banner or click the {{:vivado:getting_started:open_target_btn.png?nolink}} button in the Flow Navigator under {{:vivado:getting_started:hw_man_btn.png?nolink}}. From the dropdown that opens select {{:vivado:getting_started:auto_connect_btn.png?nolink}}. Vivado will attempt to find a hardware server running on the local machine and will connect to the device on the server.+The second method is to automatically open the target. To get to the {{:vivado:getting_started:auto_connect_btn.png?nolink}} button either open the Hardware Manager and click the {{:vivado:getting_started:open_target_banner.png?nolink}} link in the //green banner// at the top of the window or click the {{:vivado:getting_started:open_target_btn.png?nolink}} button in the //Flow Navigator// under {{:vivado:getting_started:hw_man_btn.png?nolink}}. From the drop-down that opens select {{:vivado:getting_started:auto_connect_btn.png?nolink}}. Vivado will attempt to find a hardware server running on the local machine and will connect to the device on the server.
  
 ---- ----
Line 523: Line 498:
 **Programming** **Programming**
  
-To program the device with the BIT file generated earlier either click the {{:vivado:getting_started:prog_dev_banner.png?nolink}} link in the green banner or click the {{:vivado:getting_started:prog_dev_btn.png?nolink}} button in the Flow Navigator under {{:vivado:getting_started:hw_man_btn.png?nolink}}. From the dropdown that opens select the device to program (Example: {{:vivado:getting_started:prog_dev_ex.png?nolink}}) and the following window will open:+To program the device with the bit file generated earlier, either click the {{:vivado:getting_started:prog_dev_banner.png?nolink}} link in the //green banner// at the top of the window or click the {{:vivado:getting_started:prog_dev_btn.png?nolink}} button in the //Flow Navigator// under {{:vivado:getting_started:hw_man_btn.png?nolink}}. From the drop-down that opens, select the device to program (Example: {{:vivado:getting_started:prog_dev_ex.png?nolink}}) and the following window will open:
  
-{{ :vivado:getting_started:prog_dev_diag.png?direct&500 |}}+{{ :vivado:getting_started:v2016.4:project-manager:program-device.png?direct&500 |}}
  
-The //Bitstream File// field should be filled in with the bit file generated earlier. If not, click the {{:vivado:getting_started:browse_btn.png?nolink}} button at the right end of the field and navigate to \\ //<Project Directory>/<Project Name>.runs/impl_1/// and select the bit file (Example: {{:vivado:getting_started:bit_file_ex.png?nolink}}). Now click //Program//. This will connect to the board, clear the current configuration, and program using the new bit file.+The //Bitstream File// field should be automatically filled in with the bit file generated earlier. If not, click the {{:vivado:getting_started:browse_btn.png?nolink}} button at the right end of the field and navigate to \\ //<Project Directory>/<Project Name>.runs/impl_1/// and select the bit file (Example: {{:vivado:getting_started:bit_file_ex.png?nolink}}). Now click //Program//. This will connect to the board, clear the current configuration, and program using the new bit file.
  
 ----- -----
  
-{{tag>learn programmable-logic software tutorial vivado}}+==== 10. Finished! ==== 
 + 
 +You should now see one of the LEDs on your board blinking! 
 + 
 +Be sure to visit your board's resource center for more tutorials and demo projects. A link to each resource center can be found [[/programmable-logic/start|here]]. 
 + 
 +{{tag>learn programmable-logic software tutorial vivado arty arty-a7 arty-s7 arty-z7 basys-3 cmod-a7 cmod-s7 cora-z7 genesys-2 nexys-4-ddr nexys-a7 nexys-video zybo-z7 zybo zedboard sword legacy}}