Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
vivado:getting-started-with-ipi:start [2017/10/20 16:52] – Arthur Brownvivado:getting-started-with-ipi:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
Line 1: Line 1:
-====== Getting Started with the Vivado IP Integrator ======+====== Getting Started with Vivado IP Integrator ====== 
 + 
 +<WRAP center round important 60%> 
 +For the most up to date version of this guide, please visit [[programmable-logic/guides/getting-started-with-ipi|Getting Started with Vivado and Vitis for Baremetal Software Projects]]. 
 +</WRAP> 
  
 /*FIXME: images should be collected into the correct namespace (yay)*/ /*FIXME: images should be collected into the correct namespace (yay)*/
-/*FIXME: usage of italics and bold is inconsistent*/ 
  
 {{:vivado:getting_started_with_zynq:zynq-gsg-action.png?800|}} {{:vivado:getting_started_with_zynq:zynq-gsg-action.png?800|}}
Line 10: Line 14:
   * Vivado installed. See [[learn:software:tutorials:vivado-install-guide:|this tutorial]] to install Vivado.   * Vivado installed. See [[learn:software:tutorials:vivado-install-guide:|this tutorial]] to install Vivado.
     * This guide uses version 2016.4, other versions can be used, but there may be differences.     * This guide uses version 2016.4, other versions can be used, but there may be differences.
-  * Digilent Board Files installed to handle selecting complicated configuration settings. See [[reference:software:vivado:board-files#installation|this tutorial]].+  * Digilent Board Files installed to handle selecting complicated configuration settings. See [[software:vivado:board-files#installation|this tutorial]].
   * Basic familiarity with Vivado. See [[:vivado:getting_started:|this tutorial]].   * Basic familiarity with Vivado. See [[:vivado:getting_started:|this tutorial]].
  
Line 24: Line 28:
 <WRAP column half> <WRAP column half>
 === 1.1 === === 1.1 ===
-With Vivado freshly opened, click //Create New Project//.+With Vivado freshly opened, click **Create New Project**.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 34: Line 38:
 <WRAP column half> <WRAP column half>
 === 1.2 === === 1.2 ===
-The first page of this wizard summarizes the steps involved in creating a project. Click //Next//.+The first page of this wizard summarizes the steps involved in creating a project. Click **Next**.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 49: Line 53:
 Do NOT use spaces in the project name or location path. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]]. Do NOT use spaces in the project name or location path. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]].
 </WRAP> </WRAP>
-Click //Next// to continue.+Click **Next** to continue.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 59: Line 63:
 <WRAP column half> <WRAP column half>
 === 1.4 === === 1.4 ===
-At the Select Project Type screen, choose //RTL Project// and check the //Do not specify sources at this time// box. Advanced users may want to use the other options on this screen, but they will not be covered in this guide.+At the Select Project Type screen, choose **RTL Project** and check the //Do not specify sources at this time// box. Advanced users may want to use the other options on this screen, but they will not be covered in this guide.
  
-Click //Next// to continue.+Click **Next** to continue.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 71: Line 75:
 <WRAP column half> <WRAP column half>
 === 1.5 === === 1.5 ===
-This screen selects the part targeted by the project. If Digilent's Board Files haven't yet been installed, return to the prerequisites section of this guide and follow the link to that tutorial, Vivado will then need to be restarted to load these files properly. Select the //Boards// tab, then find and select the target board from the list. Click //Next//.+This screen selects the part targeted by the project. If Digilent's Board Files haven't yet been installed, return to the prerequisites section of this guide and follow the link to that tutorial, Vivado will then need to be restarted to load these files properly. Select the **Boards** tab, then find and select the target board from the list. Click **Next**.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 81: Line 85:
 <WRAP column half> <WRAP column half>
 === 1.6 === === 1.6 ===
-This screen summarizes selections chosen in the previous screens. Click //Next// to finish opening the new project.+This screen summarizes selections chosen in the previous screens. Click **Next** to finish opening the new project.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 94: Line 98:
 <WRAP column half> <WRAP column half>
 === 2.1 === === 2.1 ===
-A more complete run-down of the standard Vivado work-flow can be found in Digilent's //Getting Started with Vivado// tutorial. This guide will be exclusively using the IP Integrator tool, which can be opened from the //Flow Navigator// on the right side of the window. Expand the //IP Integrator// tab and select //Create Block Design//.+A more complete run-down of the standard Vivado work-flow can be found in Digilent's [[:vivado:getting_started:|Getting Started with Vivado]] tutorial. This guide will be exclusively using the IP Integrator tool, which can be opened from the **Flow Navigator** on the right side of the window. Expand the **IP Integrator** tab and select **Create Block Design**.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 104: Line 108:
 <WRAP column half> <WRAP column half>
 === 2.2 === === 2.2 ===
-In the dialog box, give the block design a name. The directory location is where the block design will be stored, this can be changed, but it is recommended to leave it as //<Local to Project>//. Make sure that //Specify source set// is set to //Design Sources//.+In the dialog box, give the block design a name. The directory location is where the block design will be stored, this can be changed, but it is recommended to leave it as **<Local to Project>**. Make sure that **Specify source set** is set to **Design Sources**.
 <WRAP center round important> <WRAP center round important>
 === Important === === Important ===
 Do NOT use spaces in the block design name or directory path. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]]. Do NOT use spaces in the block design name or directory path. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]].
 </WRAP> </WRAP>
-Click //OK// to create the block design and open IPI.+Click **OK** to create the block design and open IPI.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 131: Line 135:
 <WRAP column half> <WRAP column half>
 === 3.1 === === 3.1 ===
-The //Sources// tab, highlighted in orange in the image to the right, contains several sub-tabs, of these, //Hierarchy// and //IP Sources// are the most immediately useful.+The **Sources** tab, highlighted in orange in the image to the right, contains several sub-tabs, of these, **Hierarchy** and **IP Sources** are the most immediately useful.
  
-The //Hierarchy// sub-tab shows the set of sources that exist in the project. These are split up into three groups, //Design Sources// contains the block design, and beneath that, sources for all of the IP cores or other files that are included in the block design. The //Constraints// sub-tab contains Xilinx Design Constraint (XDC) files that have been added to the project. XDC files can be used to constrain ports that have been omitted from the board file.+The **Hierarchy** sub-tab shows the set of sources that exist in the project. These are split up into three groups, **Design Sources** contains the block design, and beneath that, sources for all of the IP cores or other files that are included in the block design. The **Constraints** sub-tab contains Xilinx Design Constraint (XDC) files that have been added to the project. XDC files can be used to constrain ports that have been omitted from the board file.
  
-The //IP Sources// sub-tab shows the files generated when a new IP core has been added to the block design. Some annoying errors can be solved by right clicking on the block design in this screen and selecting //Reset Output Products// followed by //Generate Output Products//.+The **IP Sources** sub-tab shows the files generated when a new IP core has been added to the block design. Some annoying errors can be solved by right clicking on the block design in this screen and selecting **Reset Output Products** followed by **Generate Output Products**.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 145: Line 149:
 <WRAP column half> <WRAP column half>
 === 3.2 === === 3.2 ===
-When the //Design// tab is selected, a list of all input and output ports, IP core ports, and connections between IP cores is shown. Selecting an entry in this list will highlight that object in the block design diagram.+When the **Design** tab is selected, a list of all input and output ports, IP core ports, and connections between IP cores is shown. Selecting an entry in this list will highlight that object in the block design diagram.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 155: Line 159:
 <WRAP column half> <WRAP column half>
 === 3.3 === === 3.3 ===
-The //Signals// tab allows the user to view lists of all clock and reset signals in the block design. As before, selecting an entry in either of these lists will highlight that signal in the block design diagram. This tool can be useful for figuring out where data crosses clock domains in a more complicated design.+The **Signals** tab allows the user to view lists of all clock and reset signals in the block design. As before, selecting an entry in either of these lists will highlight that signal in the block design diagram. This tool can be useful for figuring out where data crosses clock domains in a more complicated design.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 165: Line 169:
 <WRAP column half> <WRAP column half>
 === 3.4 === === 3.4 ===
-The //Board// tab displays all of the external connections that Digilent has provided as part of the board file selected as part of creating the project. This tool makes connecting these ports to a design extremely straightforward. The process of connecting one of these ports will be gone through later in this guide.+The **Board** tab displays all of the external connections that Digilent has provided as part of the board file selected as part of creating the project. This tool makes connecting these ports to a design extremely straightforward. The process of connecting one of these ports will be gone through later in this guide.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 175: Line 179:
 <WRAP column half> <WRAP column half>
 === 3.5 === === 3.5 ===
-The //Properties// pane, found below the tabbed pane described above, shows the properties of the currently selected object. This pane is typically used to quickly view the clock frequency of a selected clock pin, or to change the name of an IP core or port.+The **Properties** pane, found below the tabbed pane described above, shows the properties of the currently selected object. This pane is typically used to quickly view the clock frequency of a selected clock pin, or to change the name of an IP core or port.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 185: Line 189:
 <WRAP column half> <WRAP column half>
 === 3.6 === === 3.6 ===
-Most of the upper right of the Vivado window is taken up by the //Diagram// pane. This pane displays a graphical rendition of the current block design. Many of the buttons in the toolbar to the left side of this pane will be described in Step 4 of this guide.+Most of the upper right of the Vivado window is taken up by the **Diagram** pane. This pane displays a graphical rendition of the current block design. Many of the buttons in the toolbar to the left side of this pane will be described in Step 4 of this guide.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 195: Line 199:
 <WRAP column half> <WRAP column half>
 === 3.7 === === 3.7 ===
-The //Address Editor// tab, contained in the same pane as the Diagram, describes the memory addresses that the processor can find each installed AXI peripheral at. Changing values in this pane is not recommended, except for advanced users. Errors in the block design validation process that refer to unmapped peripherals can be solved by right clicking anywhere in this pane and selecting //Auto-Assign Address//.+The **Address Editor** tab, contained in the same pane as the Diagram, describes the memory addresses that the processor can find each installed AXI peripheral at. Changing values in this pane is not recommended, except for advanced users. Errors in the block design validation process that refer to unmapped peripherals can be solved by right clicking anywhere in this pane and selecting **Auto-Assign Address**.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 205: Line 209:
 <WRAP column half> <WRAP column half>
 === 3.8 === === 3.8 ===
-The first tab of the pane at the bottom of the window is the //TCL Console//. This tool displays the scripted commands that Vivado is running whenever a change is made in the graphical interface. Scripts can be created to be run using this tool through the use of the 'source' command.+The first tab of the pane at the bottom of the window is the **TCL Console**. This tool displays the scripted commands that Vivado is running whenever a change is made in the graphical interface. Scripts can be created to be run using this tool through the use of the 'source' command.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 215: Line 219:
 <WRAP column half> <WRAP column half>
 === 3.9 === === 3.9 ===
-The //Messages// tab displays Error, Warning, Info, and Status messages created when Vivado takes different actions. These messages can also be found in the TCL Console but are presented in a relatively easy to navigate format.+The **Messages** tab displays Error, Warning, Info, and Status messages created when Vivado takes different actions. These messages can also be found in the TCL Console but are presented in a relatively easy to navigate format.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 225: Line 229:
 <WRAP column half> <WRAP column half>
 === 3.10 === === 3.10 ===
-The //Reports// tab contains a list of different reports that Vivado generates as part of the process of generating a bitstream.+The **Reports** tab contains a list of different reports that Vivado generates as part of the process of generating a bitstream.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 235: Line 239:
 <WRAP column half> <WRAP column half>
 === 3.11 === === 3.11 ===
-By selecting //Tools -> Reports -> Report IP Status// in the toolbar at the top of the Vivado window, another tab will be added to the bottom-most pane - though this will not do anything until an IP is added to the design. This //IP Status// tab displays the versions and target devices of each IP core added to the project. If an IP is not //Up-to-date//, clicking the //Upgrade All// button will reload the IP with the most recent version, or make any updates needed to make the IP work in the version of Vivado being used.+By selecting **Tools** -> **Reports** -> **Report IP Status** in the toolbar at the top of the Vivado window, another tab will be added to the bottom-most pane - though this will not do anything until an IP is added to the design. This **IP Status** tab displays the versions and target devices of each IP core added to the project. If an IP is not **Up-to-date**, clicking the **Upgrade All** button will reload the IP with the most recent version, or make any updates needed to make the IP work in the version of Vivado being used.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 243: Line 247:
  
 === 3.12 === === 3.12 ===
-The toolbar at the left of the //Diagram// pane has a large number of buttons that all do different things.+The toolbar at the left of the **Diagram** pane has a large number of buttons that all do different things.
   * //Block Design Options// ({{:vivado:getting_started_with_zynq:buttons:block-design-options.png|}}) lets the user change what is displayed and how in the diagram window.   * //Block Design Options// ({{:vivado:getting_started_with_zynq:buttons:block-design-options.png|}}) lets the user change what is displayed and how in the diagram window.
   * //Zoom In// ({{:vivado:getting_started_with_zynq:buttons:zoom-in.png|}}) zooms in the view, while maintaining the current center position.   * //Zoom In// ({{:vivado:getting_started_with_zynq:buttons:zoom-in.png|}}) zooms in the view, while maintaining the current center position.
Line 316: Line 320:
 Click **Run Block Automation** in the green bar at the top of the screen. This will launch a dialog that allows initial configuration of the Zynq block. Click **Run Block Automation** in the green bar at the top of the screen. This will launch a dialog that allows initial configuration of the Zynq block.
  
-In the Run Block Automation dialog, make sure that **FIXME** under **All Automation** in the panel to the left is selected and checked.+In the Run Block Automation dialog, make sure that **Apply Board preset** under **All Automation** in the panel to the left is checked.
  
 There are a number of different options available. For the purposes of this guide, set these options to the value found in parentheses below. There are a number of different options available. For the purposes of this guide, set these options to the value found in parentheses below.
Line 335: Line 339:
 Additional changes can be made to the Zynq block's configuration, depending on the requirements of the project. For example, the Zynq block can be used to generate new clocks of different frequencies. Select the Zynq block by clicking on it and then clicking the //Customize Block// ({{:vivado:getting_started_with_zynq:buttons:customize-block.png|}}) button, or by double-clicking on the Zynq block. Additional changes can be made to the Zynq block's configuration, depending on the requirements of the project. For example, the Zynq block can be used to generate new clocks of different frequencies. Select the Zynq block by clicking on it and then clicking the //Customize Block// ({{:vivado:getting_started_with_zynq:buttons:customize-block.png|}}) button, or by double-clicking on the Zynq block.
  
-The //Zynq Configuration// drop-down below walks through each of the screens in the Zynq's Re-Customize IP dialog.+The **Zynq Configuration** drop-down below walks through each of the screens in the Zynq's Re-Customize IP dialog.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 347: Line 351:
 <WRAP column half> <WRAP column half>
 === 4.5.1 === === 4.5.1 ===
-The page that is open when the Re-Customize dialog is launched for the Zynq block is called //Zynq Block Design//. This page displays the hardware used by the Zynq chip. Note the //I/O Peripherals// block, the check-marks display what peripherals are currently enabled. All of the information shown in this screen is available in lists in the other pages.+The page that opens when the Zynq block is re-customized is called **Zynq Block Design**. This page displays the hardware used by the Zynq chip. Note the **I/O Peripherals** block, the check-marks display what peripherals are currently enabled. All of the information shown in this screen is available in lists in the other pages.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 357: Line 361:
 <WRAP column half> <WRAP column half>
 === 4.5.3 === === 4.5.3 ===
-The //PS-PL Configuration// page allows the user to customize how the processor will communicate with the FPGA. There are several settings of particular note here. +The **PS-PL Configuration** page allows the user to customize how the processor will communicate with the FPGA. There are several settings of particular note here. 
-  * The UART baud rate settings found in the //General// drop-down are used to change the baud rate that the Zynq communicates with a computer serial port at. +  * The UART baud rate settings found in the **General** drop-down are used to change the baud rate that the Zynq communicates with a computer serial port at. 
-  * //GP/HP Slave AXI Interfaces// (General Purpose / High Performance) are used when an AXI peripheral requires control over a memory interface, this can be seen in Digilent's HDMI and Audio DMA demo projects.+  * **GP/HP Slave AXI Interfaces** (General Purpose / High Performance) are used when an AXI peripheral requires control over a memory interface, this can be seen in Digilent's HDMI and Audio DMA demo projects.
  
 </WRAP> </WRAP>
Line 370: Line 374:
 <WRAP column half> <WRAP column half>
 === 4.5.4 === === 4.5.4 ===
-The //Peripheral I/O Pins// page allows the user to enable or disable a large number of different hardware peripherals that cannot be controlled directly from the FPGA. As an example, enabling GPIO MIO allows the user to control LED 4 (LD4/MIO7) on the Zybo board.+The **Peripheral I/O Pins** page allows the user to enable or disable a large number of different hardware peripherals that cannot be controlled directly from the FPGA. As an example, enabling GPIO MIO allows the user to control LED 4 (LD4/MIO7) on the Zybo board.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 380: Line 384:
 <WRAP column half> <WRAP column half>
 === 4.5.5 === === 4.5.5 ===
-The //MIO Configuration// page shares much of its information with Peripheral I/O Pins, and allows the user to view this in a list, rather than the graphical table format.+The **MIO Configuration** page shares much of its information with Peripheral I/O Pins, and allows the user to view this in a list, rather than the graphical table format.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 390: Line 394:
 <WRAP column half> <WRAP column half>
 === 4.5.6 === === 4.5.6 ===
-The //Clock Configuration// page contains important settings that allow the user to provide additional clocks at different speeds to the FPGA, as well as tweaking the clock frequencies of several IO Peripherals. Take note of the //PL Fabric Clocks// drop-down, checking a box for one of FCLK_CLK1-3 will provide an additional clock output from the Zynq block, at or near the provided //Requested Frequency//.+The **Clock Configuration** page contains important settings that allow the user to provide additional clocks at different speeds to the FPGA, as well as tweaking the clock frequencies of several IO Peripherals. Take note of the **PL Fabric Clocks** drop-down, checking a box for one of FCLK_CLK1-3 will provide an additional clock output from the Zynq block, at or near the provided **Requested Frequency**.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 400: Line 404:
 <WRAP column half> <WRAP column half>
 === 4.5.7 === === 4.5.7 ===
-The //DDR Configuration// page contains a large number of settings about the DDR chip connected to the Zynq chip. This page alone is the reason to use the board preset brought in from Digilent's board file. Changing these settings is //not recommended//.+The **DDR Configuration** page contains a large number of settings about the DDR chip connected to the Zynq chip. This page alone is the reason to use the board preset brought in from Digilent's board file. Changing these settings is //not recommended//.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 410: Line 414:
 <WRAP column half> <WRAP column half>
 === 4.5.8 === === 4.5.8 ===
-The //Interrupts// page is another extremely useful one. To use any interrupts with the FPGA, the //Fabric Interrupts// checkbox must be checked. Many AXI IP cores can be configured to generate an interrupt on some trigger, for instance AXI GPIO cores can be set up to trigger an interrupt whenever an input changes. Checking the //IRQ_F2P// box in the //PL-PS Interrupt Ports// drop-down creates a new input port on the Zynq block which can be connected to up to sixteen individual interrupt pins via a Concat (concatenation) IP core. To use interrupts, the 'xscugic' driver for the generic interrupt controller found in the Zynq hardware must be used.+The **Interrupts** page is another extremely useful one. To use any interrupts with the FPGA, the **Fabric Interrupts** checkbox must be checked. Many AXI IP cores can be configured to generate an interrupt on some trigger, for instance AXI GPIO cores can be set up to trigger an interrupt whenever an input changes. Checking the **IRQ_F2P** box in the **PL-PS Interrupt Ports** drop-down creates a new input port on the Zynq block which can be connected to up to sixteen individual interrupt pins via a Concat (concatenation) IP core. To use interrupts, the 'xscugic' driver for the generic interrupt controller found in the Zynq hardware must be used.
  
-Additionally, interrupts generated by hardware peripherals connected using the Peripheral I/O Pins or MIO Configuration pages can be provided to the FPGA using the fields in the //PS-PL Interrupt Ports// drop-down.+Additionally, interrupts generated by hardware peripherals connected using the Peripheral I/O Pins or MIO Configuration pages can be provided to the FPGA using the fields in the **PS-PL Interrupt Ports** drop-down.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 428: Line 432:
 In the Run Connection Automation dialog's list pane, make sure that the S_AXI entry is checked and selected. In the Run Connection Automation dialog's list pane, make sure that the S_AXI entry is checked and selected.
  
-In the options pane to the right of the dialog, the clock source to run the AXI bus connecting the GPIO IP to the Zynq block can be selected. Select ///processing_system7_0/FCLK_CLK0// from the drop-down list.+In the options pane to the right of the dialog, the clock source to run the AXI bus connecting the GPIO IP to the Zynq block can be selected. Select **/processing_system7_0/FCLK_CLK0** from the drop-down list.
  
 Click **OK** to continue. Click **OK** to continue.
Line 494: Line 498:
 <WRAP column half> <WRAP column half>
 === 4.7 === === 4.7 ===
 +In the Board tab, right click on the **USB UART** and select **Connect Board Component**.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting-started-with-ipi:ipi_right_click_uart.png?800 |}}
 +</WRAP>
 +</WRAP>
 +
 +<WRAP group>
 +<WRAP column half>
 +=== 4.8 ===
 +In the **Connect Board Component** dialog, make sure to select the **AXI Uartlite** variant of the IP. 
 +
 +Click **OK** to continue.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting-started-with-ipi:ipi_axi_uartlite.png?800 |}}
 +</WRAP>
 +</WRAP>
 +
 +
 +<WRAP group>
 +<WRAP column half>
 +=== 4.9 ===
 Click **Run Connection Automation** in the green bar at the top of the block design diagram pane. Click **Run Connection Automation** in the green bar at the top of the block design diagram pane.
  
-Make sure that the //reset// entry the list on the left-hand side of the Run Connection Automation dialog is checked and selected. With this box checked, Vivado will automatically connect the reset component selected in the Board pane of the Clocking Wizard Configuration dialog to the clocking wizard, as specified in the Board tab of the Clocking Wizard configuration dialog.+Make sure that the **reset** entry the list on the left-hand side of the Run Connection Automation dialog is checked and selected. With this box checked, Vivado will automatically connect the reset component selected in the Board pane of the Clocking Wizard Configuration dialog to the clocking wizard, as specified in the Board tab of the Clocking Wizard configuration dialog.
  
 Click **OK** to continue. Click **OK** to continue.
Line 507: Line 534:
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 4.8 ===+=== 4.10 ===
 Click the **Add IP** button ({{:vivado:getting_started_with_zynq:buttons:add-ip.png|}}) and search for 'MicroBlaze'. Select **MicroBlaze** from the list of results and press **Enter** on the keyboard to continue. Click the **Add IP** button ({{:vivado:getting_started_with_zynq:buttons:add-ip.png|}}) and search for 'MicroBlaze'. Select **MicroBlaze** from the list of results and press **Enter** on the keyboard to continue.
 </WRAP> </WRAP>
Line 517: Line 544:
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 4.9 ===+=== 4.11 ===
 Click **Run Block Automation** in the green bar at the top of the screen. This will launch a dialog that allows initial configuration of the MicroBlaze and several different IP cores that are key to the function of the design. Click **Run Block Automation** in the green bar at the top of the screen. This will launch a dialog that allows initial configuration of the MicroBlaze and several different IP cores that are key to the function of the design.
  
Line 540: Line 567:
 <WRAP group> <WRAP group>
 <WRAP column half> <WRAP column half>
-=== 4.10 ===+=== 4.12 ===
 In order to connect the Uartlite and GPIO peripherals to the MicroBlaze block, click **Run Connection Automation**. In order to connect the Uartlite and GPIO peripherals to the MicroBlaze block, click **Run Connection Automation**.
 Similarly to the Run Block Automation dialog, the pane to the left of the dialog contains a list of things that can be automated. In this case, the AXI connections for axi_gpio_0 and axi_uartlite_0, as well as the external reset port of the MicroBlaze's reset clocking wizard, are available. Similarly to the Run Block Automation dialog, the pane to the left of the dialog contains a list of things that can be automated. In this case, the AXI connections for axi_gpio_0 and axi_uartlite_0, as well as the external reset port of the MicroBlaze's reset clocking wizard, are available.
Line 568: Line 595:
 Click the //Validate Design// button ({{:vivado:getting_started_with_zynq:buttons:validate-design.png|}}) to have Vivado confirm that everything looks good. Click the //Validate Design// button ({{:vivado:getting_started_with_zynq:buttons:validate-design.png|}}) to have Vivado confirm that everything looks good.
  
-Click //OK// to continue.+Click **OK** to continue.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 578: Line 605:
 <WRAP column half> <WRAP column half>
 === 5.2 === === 5.2 ===
-The last thing that needs to be done before generating a bitstream is to create a top module file. This file will take the block design and interpret it into a hardware design language so that the synthesis and implementation tools can work properly. Right click on the block design in the //Sources// tab in the pane to the left of the //Block Design// pane - this pane likely has the //Board// tab currently selected.+The last thing that needs to be done before generating a bitstream is to create a top module file. This file will take the block design and interpret it into a hardware design language so that the synthesis and implementation tools can work properly. Right click on the block design in the **Sources** tab in the pane to the left of the **Block Design** pane - this pane likely has the **Board** tab currently selected.
  
-In the right-click menu, select //Create HDL Wrapper//. In the confirmation dialog that pops up, make sure that //Let Vivado manage wrapper and auto-update// is selected in the options list. If manual changes need to be made to the wrapper file, the other option here can be selected, but it is not recommended except for advanced users. Click //OK// to have Vivado finish making the wrapper file.+In the right-click menu, select **Create HDL Wrapper**. In the confirmation dialog that pops up, make sure that //Let Vivado manage wrapper and auto-update// is selected in the options list. If manual changes need to be made to the wrapper file, the other option here can be selected, but it is not recommended except for advanced users. Click **OK** to have Vivado finish making the wrapper file.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 590: Line 617:
 <WRAP column half> <WRAP column half>
 === 5.3 === === 5.3 ===
-With a validated design and a top module, a bitstream can now be generated. The [[:vivado:getting_started:|Getting Started with Vivado]] guide explains this process in a little more detail, but for now, click the //Generate Bitstream// button in the //Flow Navigator//.+With a validated design and a top module, a bitstream can now be generated. The [[:vivado:getting_started:|Getting Started with Vivado]] guide explains this process in a little more detail, but for now, click the **Generate Bitstream** button in the **Flow Navigator**.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 601: Line 628:
 === 5.4 === === 5.4 ===
 The Launch Runs dialog that pops up has several options to choose between. Select //Launch runs on local host// to actually generate the bitstream now. The other option is to //Generate scripts only//, which will not generate a bitstream, but rather the scripts required to generate the bitstream on a different machine. The //Number of jobs// field allows the user to change how much of the resources of the computer Vivado is running on will be used. This process can take some time for complex designs, so it is recommended to devote as much of the resources as possible (typically by selecting '8'). The Launch Runs dialog that pops up has several options to choose between. Select //Launch runs on local host// to actually generate the bitstream now. The other option is to //Generate scripts only//, which will not generate a bitstream, but rather the scripts required to generate the bitstream on a different machine. The //Number of jobs// field allows the user to change how much of the resources of the computer Vivado is running on will be used. This process can take some time for complex designs, so it is recommended to devote as much of the resources as possible (typically by selecting '8').
 +
 +Click **OK** to continue.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 610: Line 639:
 <WRAP column half> <WRAP column half>
 === 5.5 === === 5.5 ===
-In the next dialog, No Implementation Results Available, Vivado will ask whether to run Synthesis and Implementation. These steps are required to generate a bitstream, so click //Yes//.+In the next dialog, No Implementation Results Available, Vivado will ask whether to run Synthesis and Implementation. These steps are required to generate a bitstream, so click **Yes**.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 620: Line 649:
 <WRAP column half> <WRAP column half>
 === 5.6 === === 5.6 ===
-Once the bitstream is generated, which may take a little while, Vivado will ask what to do next. None of the available options are required for this guide, so click //Cancel//.+Once the bitstream is generated, which may take a little while, Vivado will ask what to do next. None of the available options are required for this guide, so click **Cancel**.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 636: Line 665:
 <WRAP column half> <WRAP column half>
 === 6.1 === === 6.1 ===
-In the //File// drop-down, select //Export// then //Export to SDK//.+In the **File** drop-down, select **Export** then **Export Hardware**. This function collects all of the files that SDK needs to program the FPGA and control the hardware instantiated in the design and puts them all into one place.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 646: Line 675:
 <WRAP column half> <WRAP column half>
 === 6.2 === === 6.2 ===
-Make sure that the //Include Bitstream// box is checked, so that the FPGA can be programmed from Vivado SDK. The //Export Location// is //<Local To Project>// by default. This means that Vivado will create a new directory in the project directory called '<project name>.sdk' where the hardware handoff file - named '<HDL wrapper name>.hdf' - can be found. If a different location is chosen for the hardware handoff file, make sure to remember where it is.+Make sure that the **Include Bitstream** box is checked, so that the FPGA can be programmed from Vivado SDK. The **Export Location** is **<Local To Project>** by default. This means that Vivado will create a new directory in the project directory called '<project name>.sdk' where the hardware handoff file - named '<HDL wrapper name>.hdf' - can be found. If a different location is chosen for the hardware handoff file, make sure to remember where it is.
 <WRAP center round important> <WRAP center round important>
 === Important === === Important ===
 Do NOT use spaces in the export location path. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]]. Do NOT use spaces in the export location path. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]].
 </WRAP> </WRAP>
-Click //OK// to continue.+Click **OK** to continue.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 661: Line 690:
 <WRAP column half> <WRAP column half>
 === 6.3 === === 6.3 ===
-Just below //Export// in the //File// drop-down, select //Launch SDK//.+Just below **Export** in the **File** drop-down, select **Launch SDK**.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 671: Line 700:
 <WRAP column half> <WRAP column half>
 === 6.4 === === 6.4 ===
-The dialog that pops up will tell Vivado where to find the exported files, as well as where to create the SDK workspace. Make sure to set //Exported Location// to the location chosen earlier. The //Workspace// field is //<Local To Project>// by default. This means that Vivado will use a directory in the project directory called '<project name>.sdk' to store the sources and projects created in Vivado SDK. If this directory does not exist, it will be created. This location can be changed if somewhere else is desired, but it is recommended to leave it as is.+The dialog that pops up will tell Vivado where to find the exported files, as well as where to create the SDK workspace. Make sure to set **Exported Location** to the location chosen earlier. The **Workspace** field is **<Local To Project>** by default. This means that Vivado will use a directory in the project directory called '<project name>.sdk' to store the sources and projects created in Vivado SDK. If this directory does not exist, it will be created. This location can be changed if somewhere else is desired, but it is recommended to leave it as is.
 <WRAP center round important> <WRAP center round important>
 === Important === === Important ===
 Do NOT use spaces in the workspace path. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]]. Do NOT use spaces in the workspace path. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]].
 </WRAP> </WRAP>
-Click //OK// to continue.+Click **OK** to continue.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 691: Line 720:
 === 7.1 === === 7.1 ===
 Vivado SDK will now launch, and will import the hardware definition, creating a workspace containing only a hw_platform project. This project contains the files exported from Vivado. There are only a few relevant panes to this guide. Vivado SDK will now launch, and will import the hardware definition, creating a workspace containing only a hw_platform project. This project contains the files exported from Vivado. There are only a few relevant panes to this guide.
-  * The //Project Explorer//, found to the left hand side of the window, displays all projects imported into the workspace, each of which can be expanded to view the sources, scripts, and other files that they contain. +  * The **Project Explorer**, found to the left hand side of the window, displays all projects imported into the workspace, each of which can be expanded to view the sources, scripts, and other files that they contain. 
-  * The //File View//, directly in the center of the window, displays currently opened files. Upon launch of SDK, an overview of the hardware platform exported from Vivado is displayed. Note the AXI GPIO cell contained in the Address Map, and the corresponding entry in the list of IP blocks.+  * The **File View**, directly in the center of the window, displays currently opened files. Upon launch of SDK, an overview of the hardware platform exported from Vivado is displayed. Note the AXI GPIO cell contained in the Address Map, and the corresponding entry in the list of IP blocks.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 702: Line 731:
 <WRAP column half> <WRAP column half>
 === 7.2 === === 7.2 ===
-In order to create a project to store C source code, click //File// in the top toolbar, followed by //New > Application Project//.+In order to create a project to store C source code, click **File** in the top toolbar, followed by **New** -> **Application Project**.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 712: Line 741:
 <WRAP column half> <WRAP column half>
 === 7.3 === === 7.3 ===
-In the New Project dialog, give the project a name, and make sure that //C// is selected as the //Language// in the //Target Software// box.+In the New Project dialog, give the project a name, and make sure that //C// is selected as the **Language** in the **Target Software** box.
 <WRAP center round important> <WRAP center round important>
 === Important === === Important ===
 Do NOT use spaces in the project name. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]]. Do NOT use spaces in the project name. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]].
 </WRAP> </WRAP>
-Click //Next// to continue.+Click **Next** to continue.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 727: Line 756:
 <WRAP column half> <WRAP column half>
 === 7.4 === === 7.4 ===
-From the list of Available Templates, select //Empty Application//, then click //Finish//.+From the list of Available Templates, select **Empty Application**, then click **Finish**.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 737: Line 766:
 <WRAP column half> <WRAP column half>
 === 7.5 === === 7.5 ===
-Expand the newly created project - not its board support package - then expand the 'src' folder. Right-click on the 'src' folder and select //New > Source File// from the menu.+Expand the newly created project - not its board support package - then expand the 'src' folder. Right-click on the 'src' folder and select **New -> Source File** from the menu.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 747: Line 776:
 <WRAP column half> <WRAP column half>
 === 7.6 === === 7.6 ===
-Name the new source file 'main.c', then click //Finish//.+Name the new source file //main.c//, then click **Finish**.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 757: Line 786:
 <WRAP column half> <WRAP column half>
 === 7.7 === === 7.7 ===
-The new main file will now open in the file view pane. Copy-Paste the code to the right into this file, then hit //Ctrl-S// to save the file and build the project.+The new main file will now open in the file view pane. Copy-Paste the code to the right into this file, then hit **Ctrl-S** to save the file and build the project.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 807: Line 836:
 <WRAP column half> <WRAP column half>
 === 8.1 === === 8.1 ===
-From the top toolbar, select //Xilinx Tools//, then //Program FPGA//.+From the top toolbar, select **Xilinx Tools**, then **Program FPGA**.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 817: Line 846:
 <WRAP column half> <WRAP column half>
 === 8.2 === === 8.2 ===
-Leave all of the settings in the Program FPGA dialog as they are, then click //Program//. This only programs the FPGA, not the processor, so that is next.+Leave all of the settings in the Program FPGA dialog as they are, then click **Program**. This only programs the FPGA, not the processor, so that is next.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 827: Line 856:
 <WRAP column half> <WRAP column half>
 === 8.3 === === 8.3 ===
-Right click on the application project in the //Project Explorer//, then select //Run As > Launch on Hardware (System Debugger)//.+Right click on the application project in the **Project Explorer**, then select **Run As -> Launch on Hardware (System Debugger)**.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
Line 860: Line 889:
 ==== Next Steps ==== ==== Next Steps ====
  
-Examples of more complicated IPI designs are linked from the target board's resource center, which can be found in [[:reference:programmable-logic:|this list]].+Examples of more complicated IPI designs - including examples of the use of DDR memory in MicroBlaze designs - are linked from the target board's resource center, which can be found in [[programmable-logic:|this list]]. 
  
 ----- -----
  
-{{tag>learn programmable-logic software tutorial vivado arty arty-z7 arty-s7 basys-3 cmod-a7 cmod-s7 genesys-2 nexys-4 nexys-4-ddr nexys-video zedboard zybo zybo-z7 }}+{{tag>learn programmable-logic software tutorial vivado arty arty-a7 arty-s7 arty-z7 basys-3 cmod-a7 cmod-s7 cora-z7 genesys-2 nexys-4 nexys-4-ddr nexys-a7 nexys-video zedboard zybo zybo-z7 sword legacy }}