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test-and-measurement:analog-discovery-studio:cmod-s7-demo [2021/10/13 21:45] – Arthur Browntest-and-measurement:analog-discovery-studio:cmod-s7-demo [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 2. Open Adept, and connect to the Cmod S7. Under the **Config** tab, click **Browse**, then navigate to the file "top.bit" in the folder extracted from the demo archive. Click the **Program** button to load the bit file onto the FPGA. 2. Open Adept, and connect to the Cmod S7. Under the **Config** tab, click **Browse**, then navigate to the file "top.bit" in the folder extracted from the demo archive. Click the **Program** button to load the bit file onto the FPGA.
  
-**Note:** //Alternatively, the Cmod S7's flash can be programmed using Xilinx's [[https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2019-1.html|Vivado 2019.1]]. In Vivado's TCL Console, sourcing the "program_flash.tcl" script will connect to the Cmod S7 and program the "top.bin" file into flash, so that the demo will begin running whenever the Cmod S7 is powered on.//+**Note:** //Alternatively, the Cmod S7's flash can be programmed using Xilinx Vivado 2019.1. In Vivado's TCL Console, sourcing the "program_flash.tcl" script will connect to the Cmod S7 and program the "top.bin" file into flash, so that the demo will begin running whenever the Cmod S7 is powered on.//
  
 **Note:** //The full Vivado project used in this demo, written primarily in Verilog, is hosted on Github in this [[https://github.com/Digilent/Analog-Discovery-Studio-Cmod-S7-SPI|repository]]. In addition, a release is contained within the demo archive linked above.// **Note:** //The full Vivado project used in this demo, written primarily in Verilog, is hosted on Github in this [[https://github.com/Digilent/Analog-Discovery-Studio-Cmod-S7-SPI|repository]]. In addition, a release is contained within the demo archive linked above.//