Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Next revision		Previous revision
programming_solutions:refmanual [2015/06/26 21:49] – created Marthaprogramming_solutions:refmanual [2022/10/04 11:38] (current) – external edit 127.0.0.1
Line 4: Line 4:
 {{ :programming_solutions:jtag_hs1:ove1.png?300|}} {{ :programming_solutions:jtag_hs1:ove1.png?300|}}
  
-The JTAG-HS1 programming cable is a high-speed programming solution for Xilinx FPGAs. It is fully compatible will all Xilinx tools, and can be seamlessly driven from iMPACT, Chipscope, and EDK. The HS-1 attaches to target boards using Digilent’s 6-pin, 100-mil spaced programming header, or Xilinx’s 2x7, 2mm connector (using the included adaptor).+The JTAG-HS1 programming cable is a high-speed programming solution for Xilinx(r) FPGAs. It is fully compatible will all Xilinx tools, and can be seamlessly driven from iMPACT(tm), ChipScope(tm), and EDK. The HS-1 attaches to target boards using Digilent’s 6-pin, 100-mil spaced programming header, or Xilinx’s 2x7, 2mm connector (using the included adaptor).
  
 The JTAG-HS1 is powered from a PC’s USB port, and will be recognized as a Digilent programming cable when connected to a PC, whether or not it is attached to the target board. A separate Vdd pin is provided on the HS1 to supply JTAG signal buffers. The high speed, 24mA, three-state buffers allow target boards to drive the HS1 with signal voltages from 1.8V to 5V, with bus speeds of up to 30MBit/sec. The HS1’s Vdd pin must be tied to the same voltage supply that drives the JTAG port on the FPGA. The JTAG-HS1 is powered from a PC’s USB port, and will be recognized as a Digilent programming cable when connected to a PC, whether or not it is attached to the target board. A separate Vdd pin is provided on the HS1 to supply JTAG signal buffers. The high speed, 24mA, three-state buffers allow target boards to drive the HS1 with signal voltages from 1.8V to 5V, with bus speeds of up to 30MBit/sec. The HS1’s Vdd pin must be tied to the same voltage supply that drives the JTAG port on the FPGA.