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programmable-logic:zybo-z7:reference-manual [2022/03/25 15:43] – Add power supply changes for ethernet pcn Arthur Brownprogrammable-logic:zybo-z7:reference-manual [2022/10/04 04:38] (current) – external edit 127.0.0.1
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 Design resources, example projects, and tutorials are available for download at the [[programmable-logic:zybo-z7:start|Zybo Z7 Resource Center]]. Design resources, example projects, and tutorials are available for download at the [[programmable-logic:zybo-z7:start|Zybo Z7 Resource Center]].
  
-Zynq platforms are well-suited to be embedded Linux targets, and Zybo Z7 is no exception. Digilent currently does not provide a Petalinux example for this product, however one will be available in the near future on the [[programmable-logic:zybo-z7:start|Zybo Z7 Resource Center]].+Zynq platforms are well-suited to be embedded Linux targets, and Zybo Z7 is no exception. A Petalinux image for the board targeting PetaLinux 2017.4 is available through the [[programmable-logic:zybo-z7:start|Zybo Z7 Resource Center]].
  
 The Zybo Z7 can also be used in Xilinx's SDSoC environment, which allows you to design FPGA accelerated programs and video pipelines with ease in an entirely C/C++ environment. For more information on SDSoC, see the [[https://www.xilinx.com/products/design-tools/software-zone/sdsoc.html|Xilinx SDSoC Site]]. Digilent will be releasing a video capable platform with Linux and OpenCV support in the near future. Note that due to the smaller FPGA in the Zybo Z7-10, only very basic video processing demos will be included with that platform. Digilent recommends the Zybo Z7-20 for those interested in video processing. The Zybo Z7 can also be used in Xilinx's SDSoC environment, which allows you to design FPGA accelerated programs and video pipelines with ease in an entirely C/C++ environment. For more information on SDSoC, see the [[https://www.xilinx.com/products/design-tools/software-zone/sdsoc.html|Xilinx SDSoC Site]]. Digilent will be releasing a video capable platform with Linux and OpenCV support in the near future. Note that due to the smaller FPGA in the Zybo Z7-10, only very basic video processing demos will be included with that platform. Digilent recommends the Zybo Z7-20 for those interested in video processing.
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 The PS consists of many components, including the Application Processing Unit (APU, which includes 2 Cortex-A9 processors), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory controller, and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins). Peripheral controllers that do not have their inputs and outputs connected to MIO pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers that are addressable in the processors’ memory space. The programmable logic is also connected to the interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain addressable control registers. Furthermore, cores implemented in the PL can trigger interrupts to the processors and perform DMA accesses to DDR3 memory. The PS consists of many components, including the Application Processing Unit (APU, which includes 2 Cortex-A9 processors), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory controller, and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins). Peripheral controllers that do not have their inputs and outputs connected to MIO pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers that are addressable in the processors’ memory space. The programmable logic is also connected to the interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain addressable control registers. Furthermore, cores implemented in the PL can trigger interrupts to the processors and perform DMA accesses to DDR3 memory.
  
-There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description, refer to the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]]. +There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description, refer to the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]]. 
  
 The table below depicts the external components connected to the MIO pins of the Zybo Z7. The Vivado board files found on the [[programmable-logic:zybo-z7:start|Zybo Z7 Resource Center]] can be used to properly configure the PS to work with these peripherals. It is also possible to use the example projects found on the resource center as a starting point for your own designs. The table below depicts the external components connected to the MIO pins of the Zybo Z7. The Vivado board files found on the [[programmable-logic:zybo-z7:start|Zybo Z7 Resource Center]] can be used to properly configure the PS to work with these peripherals. It is also possible to use the example projects found on the resource center as a starting point for your own designs.
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 ===== 1 Power Supplies ===== ===== 1 Power Supplies =====
- 
-**Note:** //The power-on sequencing has been changed in revision D.0 of the board. This section has not yet been updated.// 
  
 The Zybo Z7 power circuitry was carefully designed to meet the requirements of the Zynq-7000 and all other peripherals while also providing flexible input supply options. An overview of the power circuit is shown in Figure 1.1. The Zybo Z7 power circuitry was carefully designed to meet the requirements of the Zynq-7000 and all other peripherals while also providing flexible input supply options. An overview of the power circuit is shown in Figure 1.1.
  
-{{:programmable-logic:zybo-z7:zybo-z7-power-rev-d0.png?700|}} +{{ :programmable-logic:zybo-z7:zybo-z7-power-d0.png?800 |}} 
-//Figure 1.1. Power circuit overview//+<html><center></html>//Figure 1.1. Power circuit overview//<html></center></html>
  
 All on-board power supplies are enabled or disabled by the power switch (SW4). The power indicator LED (LD13, labeled PGOOD) is on when all the supply rails reach their nominal voltage. A proper power cycle requires the power switch to stay in the OFF position for at least 1 second. All on-board power supplies are enabled or disabled by the power switch (SW4). The power indicator LED (LD13, labeled PGOOD) is on when all the supply rails reach their nominal voltage. A proper power cycle requires the power switch to stay in the OFF position for at least 1 second.
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 The supply rails downstream are daisy-chained to follow the Xilinx-recommended start-up sequence. Flicking the power switch (SW4) will enable the 1.0V rail, which enables the 1.8V digital supply rail, which in turn enables the I/O supply rails 3.3V and 1.35V. The 1.25V reference and 1.8V analog supply ramp together with the 3.3V rail. Once all the channels of the ADP5052 (IC25) supply reach regulation, the PGOOD signal will assert, enabling the 3.3V audio supply and 1.8V I/O power rail, lighting up the power LED (LD13), and de-asserting the Power-On Reset signal (PS_POR_B) of the Zynq. The supply rails downstream are daisy-chained to follow the Xilinx-recommended start-up sequence. Flicking the power switch (SW4) will enable the 1.0V rail, which enables the 1.8V digital supply rail, which in turn enables the I/O supply rails 3.3V and 1.35V. The 1.25V reference and 1.8V analog supply ramp together with the 3.3V rail. Once all the channels of the ADP5052 (IC25) supply reach regulation, the PGOOD signal will assert, enabling the 3.3V audio supply and 1.8V I/O power rail, lighting up the power LED (LD13), and de-asserting the Power-On Reset signal (PS_POR_B) of the Zynq.
  
-Each power supply uses a soft-start ramp of 1-10ms to limit in-rush current. There is an additional delay of at least 130ms after the power rails reach regulation and before the Power-On Reset signal de-assert to allow for the PS_CLK (IC22) to stabilize. +Each power supply uses a soft-start ramp of 1-10ms to limit in-rush current. There is an additional delay of at least 130ms after the power rails reach regulation and before the Power-On Reset signal de-assert to allow for the PS_CLK (IC22) to stabilize. Further delay, typically 120 ms, is added before the deassert of the Zynq Power-On Reset to ensure that the Ethernet PHY, powered by the VCC1V8_IO rail and internally regulated, is ready before Zynq projects (without boot optimization) finish booting.
  
 ==== 1.4 Current Monitoring ==== ==== 1.4 Current Monitoring ====
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 **Stage 2**  **Stage 2** 
  
-The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple “Hello World” design, to a Second Stage Boot loader used to boot an operating system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple “Hello World” design, to a Second Stage Boot loader used to boot an operating system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
  
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 Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specific to the Zybo Z7 memory interface PCB design.  Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specific to the Zybo Z7 memory interface PCB design. 
  
-For more details on memory controller operation, refer to the Xilinx [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+For more details on memory controller operation, refer to the Xilinx [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
 ---- ----
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   * U-boot and Linux kernel built using the “jedec,spi-nor” compatibility string for the flash node needs no changes, as the part is identified during probe. If the old way of specifying a fixed part is used, it is recommended that the compatibility string is replaced with “jedec,spi-nor”.   * U-boot and Linux kernel built using the “jedec,spi-nor” compatibility string for the flash node needs no changes, as the part is identified during probe. If the old way of specifying a fixed part is used, it is recommended that the compatibility string is replaced with “jedec,spi-nor”.
  
-**Note:** //Refer to the manufacturers' datasheets[([[https://www.infineon.com/dgdl/Infineon-S25FL128S_S25FL256S_128_Mb_(16_MB)_256_Mb_(32_MB)_3.0V_SPI_Flash_Memory-DataSheet-v18_00-EN.pdf|S25FL128S Datasheet]])][([[https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.pdf|W25Q128JV Datasheet]])] and Zynq Technical Reference Manual[([[https://www.xilinx.com/content/dam/xilinx/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Xilinx Zynq Technical Reference Manual (UG585)]])] for more information.//+**Note:** //Refer to the manufacturers' datasheets[([[https://www.infineon.com/dgdl/Infineon-S25FL128S_S25FL256S_128_Mb_(16_MB)_256_Mb_(32_MB)_3.0V_SPI_Flash_Memory-DataSheet-v18_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecfb6a64a17|S25FL128S Datasheet]])][([[https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.pdf|W25Q128JV Datasheet]])] and Zynq Technical Reference Manual[([[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Xilinx Zynq Technical Reference Manual (UG585)]])] for more information.//
  
 ~~REFNOTES~~ ~~REFNOTES~~
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 ===== 8 microSD Slot ===== ===== 8 microSD Slot =====
  
-The Zybo Z7 provides a microSD slot (J4) for non-volatile external memory storage as well as booting the Zynq. The slot is wired to Bank 1/501 MIO[40-45], and also includes a card detect signal attached to MIO 47. On the PS side peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 8.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference Manual]], SDIO host mode is the only mode supported.+The Zybo Z7 provides a microSD slot (J4) for non-volatile external memory storage as well as booting the Zynq. The slot is wired to Bank 1/501 MIO[40-45], and also includes a card detect signal attached to MIO 47. On the PS side peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 8.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference Manual]], SDIO host mode is the only mode supported.
  
 | **Signal Name**  | **Description**  | **Zynq Pin**  | **SD Slot Pin**  | | **Signal Name**  | **Description**  | **Zynq Pin**  | **SD Slot Pin**  |
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 //Figure 15.2. Attaching a Pcam// //Figure 15.2. Attaching a Pcam//
  
-The MIPI CSI-2 bus is passively terminated on the Zybo Z7 and connected directly to the Zynq PL. The guidelines described in Xilinx application note [[https://www.xilinx.com/support/documentation/application_notes/xapp894-d-phy-solutions.pdf| XAPP894 D-PHY solutions]] were followed in order to implement a compatible D-PHY receiver using the Zynq. The interface is tested to operate at up to 672 Mbps on each lane. Speeds up to 950 Mbps on each lane are possible based on the Zynq-7000 timing specifications, however they are not validated on the Zybo Z7.+The MIPI CSI-2 bus is passively terminated on the Zybo Z7 and connected directly to the Zynq PL. The guidelines described in Xilinx application note [[https://docs.xilinx.com/v/u/en-US/xapp894-d-phy-solutions| XAPP894 D-PHY solutions]] were followed in order to implement a compatible D-PHY receiver using the Zynq. The interface is tested to operate at up to 672 Mbps on each lane. Speeds up to 950 Mbps on each lane are possible based on the Zynq-7000 timing specifications, however they are not validated on the Zybo Z7.
  
 A [[https://www.xilinx.com/products/intellectual-property/ef-di-mipi-csi-rx.html|MIPI CSI-2 Receiver IP core]] is available from Xilinx, and includes embedded Linux support. It requires a license in order to use, however it is possible to obtain an evaluation license from Xilinx for free. A [[https://www.xilinx.com/products/intellectual-property/ef-di-mipi-csi-rx.html|MIPI CSI-2 Receiver IP core]] is available from Xilinx, and includes embedded Linux support. It requires a license in order to use, however it is possible to obtain an evaluation license from Xilinx for free.
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 Although we strive to provide perfect products, we are not infallible. The Zybo Z7 is subject to the limitations below. Although we strive to provide perfect products, we are not infallible. The Zybo Z7 is subject to the limitations below.
 ^ Product Name  ^ Variant  ^ Revision  ^ Problem                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ^ Status        ^ ^ Product Name  ^ Variant  ^ Revision  ^ Problem                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ^ Status        ^
-| Zybo Z7       | All      | All       | Negative CK-to-DQS delays in the board files are causing critical warnings in Vivado >2017.4:\\ [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values. \\ \\ The negative values are due to CK trace being shorter than any of the four DQS traces.\\ \\ In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Zybo (Z7) was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Zybo (Z7)s shipped to customers are functionally tested and pass the DDR3 calibration process. \\ \\ Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: https://www.xilinx.com/support/answers/53039.html. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. \\ \\ To silence the warnings, zero board delays can be set in Processing System configuration. The calibration algorithm seems to be using zero starting values anyway when negative delays are given.  | will not fix  |+| Zybo Z7       | All      | All       | Negative CK-to-DQS delays in the board files are causing critical warnings in Vivado >2017.4:\\ [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values. \\ \\ The negative values are due to CK trace being shorter than any of the four DQS traces.\\ \\ In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Zybo (Z7) was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Zybo (Z7)s shipped to customers are functionally tested and pass the DDR3 calibration process. \\ \\ Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: [[https://support.xilinx.com/s/article/53039]]. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. \\ \\ To silence the warnings, zero board delays can be set in Processing System configuration. The calibration algorithm seems to be using zero starting values anyway when negative delays are given.  | will not fix  |
 {{tag>rm doc zybo-z7}} {{tag>rm doc zybo-z7}}