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programmable-logic:zybo-z7:reference-manual [2022/03/18 15:14] – Arthur Brownprogrammable-logic:zybo-z7:reference-manual [2022/10/04 04:38] (current) – external edit 127.0.0.1
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 Design resources, example projects, and tutorials are available for download at the [[programmable-logic:zybo-z7:start|Zybo Z7 Resource Center]]. Design resources, example projects, and tutorials are available for download at the [[programmable-logic:zybo-z7:start|Zybo Z7 Resource Center]].
  
-Zynq platforms are well-suited to be embedded Linux targets, and Zybo Z7 is no exception. Digilent currently does not provide a Petalinux example for this product, however one will be available in the near future on the [[programmable-logic:zybo-z7:start|Zybo Z7 Resource Center]].+Zynq platforms are well-suited to be embedded Linux targets, and Zybo Z7 is no exception. A Petalinux image for the board targeting PetaLinux 2017.4 is available through the [[programmable-logic:zybo-z7:start|Zybo Z7 Resource Center]].
  
 The Zybo Z7 can also be used in Xilinx's SDSoC environment, which allows you to design FPGA accelerated programs and video pipelines with ease in an entirely C/C++ environment. For more information on SDSoC, see the [[https://www.xilinx.com/products/design-tools/software-zone/sdsoc.html|Xilinx SDSoC Site]]. Digilent will be releasing a video capable platform with Linux and OpenCV support in the near future. Note that due to the smaller FPGA in the Zybo Z7-10, only very basic video processing demos will be included with that platform. Digilent recommends the Zybo Z7-20 for those interested in video processing. The Zybo Z7 can also be used in Xilinx's SDSoC environment, which allows you to design FPGA accelerated programs and video pipelines with ease in an entirely C/C++ environment. For more information on SDSoC, see the [[https://www.xilinx.com/products/design-tools/software-zone/sdsoc.html|Xilinx SDSoC Site]]. Digilent will be releasing a video capable platform with Linux and OpenCV support in the near future. Note that due to the smaller FPGA in the Zybo Z7-10, only very basic video processing demos will be included with that platform. Digilent recommends the Zybo Z7-20 for those interested in video processing.
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 The PS consists of many components, including the Application Processing Unit (APU, which includes 2 Cortex-A9 processors), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory controller, and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins). Peripheral controllers that do not have their inputs and outputs connected to MIO pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers that are addressable in the processors’ memory space. The programmable logic is also connected to the interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain addressable control registers. Furthermore, cores implemented in the PL can trigger interrupts to the processors and perform DMA accesses to DDR3 memory. The PS consists of many components, including the Application Processing Unit (APU, which includes 2 Cortex-A9 processors), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory controller, and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins). Peripheral controllers that do not have their inputs and outputs connected to MIO pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers that are addressable in the processors’ memory space. The programmable logic is also connected to the interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain addressable control registers. Furthermore, cores implemented in the PL can trigger interrupts to the processors and perform DMA accesses to DDR3 memory.
  
-There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description, refer to the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]]. +There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description, refer to the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]]. 
  
 The table below depicts the external components connected to the MIO pins of the Zybo Z7. The Vivado board files found on the [[programmable-logic:zybo-z7:start|Zybo Z7 Resource Center]] can be used to properly configure the PS to work with these peripherals. It is also possible to use the example projects found on the resource center as a starting point for your own designs. The table below depicts the external components connected to the MIO pins of the Zybo Z7. The Vivado board files found on the [[programmable-logic:zybo-z7:start|Zybo Z7 Resource Center]] can be used to properly configure the PS to work with these peripherals. It is also possible to use the example projects found on the resource center as a starting point for your own designs.
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 The Zybo Z7 power circuitry was carefully designed to meet the requirements of the Zynq-7000 and all other peripherals while also providing flexible input supply options. An overview of the power circuit is shown in Figure 1.1. The Zybo Z7 power circuitry was carefully designed to meet the requirements of the Zynq-7000 and all other peripherals while also providing flexible input supply options. An overview of the power circuit is shown in Figure 1.1.
  
-{{ :reference:programmable-logic:zybo-z7:zybo-z7-power.png?700 |}} +{{ :programmable-logic:zybo-z7:zybo-z7-power-d0.png?800 |}} 
- +<html><center></html>//Figure 1.1. Power circuit overview//<html></center></html>
-//Figure 1.1. Power circuit overview//+
  
 All on-board power supplies are enabled or disabled by the power switch (SW4). The power indicator LED (LD13, labeled PGOOD) is on when all the supply rails reach their nominal voltage. A proper power cycle requires the power switch to stay in the OFF position for at least 1 second. All on-board power supplies are enabled or disabled by the power switch (SW4). The power indicator LED (LD13, labeled PGOOD) is on when all the supply rails reach their nominal voltage. A proper power cycle requires the power switch to stay in the OFF position for at least 1 second.
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 The Zybo Z7 can be powered from several different sources. Jumper JP6 (near the power switch) determines which power source is used. There are three valid configurations for this jumper corresponding to the three powering options: USB, wall wart supply with barrel jack, and battery pack. Figure 1.1 depicts all three, and a diagram on the board silkscreen does as well. The Zybo Z7 can be powered from several different sources. Jumper JP6 (near the power switch) determines which power source is used. There are three valid configurations for this jumper corresponding to the three powering options: USB, wall wart supply with barrel jack, and battery pack. Figure 1.1 depicts all three, and a diagram on the board silkscreen does as well.
  
-The recommended power source is an external power supply (such as a wall-wart) with a barrel jack connector (also known as a coaxial power connector). The supply must use a center-positive 2.1mm internal-diameter plug and deliver between 4.5V to 5.5V DC. It should also be able to output at least 2.5 A (12.5 Watts) in order to support power hungry Zynq projects and external peripherals. To use an external supply with a barrel jack, plug it into the power jack (J17), set jumper JP6 to “WALL”, and then set SW4 to "ON". Suitable supplies can be purchased from the Digilent website or Digilent distributors, as well as popular electronics vendors. +The recommended power source is an external power supply (such as a wall-wart) with a barrel jack connector (also known as a coaxial power connector). The supply must use a center-positive 2.1 mm internal-diameter plug and deliver between 4.5 V to 5.5 V DC. It should also be able to output at least 2.5 A (12.5 Watts) in order to support power-hungry Zynq projects and external peripherals. To use an external supply with a barrel jack, plug it into the power jack (J17), set jumper JP6 to “WALL”, and then set SW4 to "ON". Suitable supplies can be purchased from the Digilent website or Digilent distributors, as well as popular electronics vendors. 
  
-An external power source, such as a battery pack, that does not have a suitable barrel jack connector can still be used by wiring it’s positive terminal to the center pin of JP6 and the negative terminal to the pin labeled J16 next to JP6. The external supply must still meet the same voltage requirements as a supply attached to the barrel jack.+An external power source, such as a battery pack, that does not have a suitable barrel jack connector can still be used by wiring its positive terminal to the center pin of JP6 and the negative terminal to the pin labeled J16 next to JP6. The external supply must still meet the same voltage requirements as a supply attached to the barrel jack.
  
-It is also possible to power the Zybo Z7 from the USB programming port (J12), however the Zybo Z7 often requires more current than the 0.5 A of current that is allowed by a USB 2.0 device. If this limit is exceeded, many USB hosts will begin to droop the voltage briefly until the Zybo Z7 resets, dropping current consumption into acceptable ranges. To help prevent this, a USB host port should be chosen that can support higher current (often referred to as a "fast charging USB port" or similar by laptop/PC vendors). Many USB battery packs and wall supplies will also support higher current draws. Even when attached to a host capable of providing more current, the Zybo Z7 will limit itself to .75 A (typ), and will reset if this current is reached. If you experience your project resetting (indicated by a brief flicker on the PGOOD LED and the DONE LED turning off) while powered from a high current USB port, you will either need to lower the power consumption of your project or use an external power source with a barrel jack. +It is also possible to power the Zybo Z7 from the USB programming port (J12), however, the Zybo Z7 often requires more current than the 0.5 A of current that is allowed by a USB 2.0 device. If this limit is exceeded, many USB hosts will begin to drop the voltage briefly until the Zybo Z7 resets, dropping current consumption into acceptable ranges. To help prevent this, a USB host port should be chosen that can support higher current (often referred to as a "fast charging USB port" or similar by laptop/PC vendors). Many USB battery packs and wall supplies will also support higher current draws. Even when attached to a host capable of providing more current, the Zybo Z7 will limit itself to .75 A (typ), and will reset if this current is reached. If you experience your project resetting (indicated by a brief flicker on the PGOOD LED and the DONE LED turning off) while powered from a high current USB port, you will either need to lower the power consumption of your project or use an external power source with a barrel jack. 
  
 For reference, we found that the out of box demo loaded on the Zybo Z7 at the factory consumes about 0.5 A from the input power source. More demanding applications, including any that drive multiple peripheral boards or other USB devices, will likely draw more.  For reference, we found that the out of box demo loaded on the Zybo Z7 at the factory consumes about 0.5 A from the input power source. More demanding applications, including any that drive multiple peripheral boards or other USB devices, will likely draw more. 
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 Table 1.1.1 provides an overview of the power input specifications for the Zybo Z7. Table 1.1.1 provides an overview of the power input specifications for the Zybo Z7.
 +
 +//Table 1.1.1. Zybo Z7 Power Input Specifications//
  
 ^ Connector Type  ^ JP6 Configuration  ^ Connector Label  ^ Schematic net name  ^ Min/Rec/Max Voltage (V)  ^ Min Current Limit (A)  ^ ^ Connector Type  ^ JP6 Configuration  ^ Connector Label  ^ Schematic net name  ^ Min/Rec/Max Voltage (V)  ^ Min Current Limit (A)  ^
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 | USB             | USB                | J12              | VBUS                | See USB specification    | 0.73                   | | USB             | USB                | J12              | VBUS                | See USB specification    | 0.73                   |
  
-//Table 1.1.1. Zybo Z7 Power Input Specifications// 
  
 ==== 1.2 Power Specifications ==== ==== 1.2 Power Specifications ====
  
 Table 1.2.1 describes the characteristics the Zybo Z7's on-board power rails. It can be used to estimate power consumption for a project, or determine how much current attached peripherals can draw before being limited.   Table 1.2.1 describes the characteristics the Zybo Z7's on-board power rails. It can be used to estimate power consumption for a project, or determine how much current attached peripherals can draw before being limited.  
 +
 +//Table 1.2.1. Zybo Z7 Power Rail Specifications//
  
 ^ Net name   ^ Upstream net name  ^ Power IC Type     ^ Power IC Label  ^ Min/Typ/Max Voltage (V)  ^ Max. Current     ^ Major Devices and Connectors     ^ ^ Net name   ^ Upstream net name  ^ Power IC Type     ^ Power IC Label  ^ Min/Typ/Max Voltage (V)  ^ Max. Current     ^ Major Devices and Connectors     ^
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 | VCC1V0     | VCC5V0             | Buck              | IC25            | 1.0V +-5%                | 2.1A             | FPGA, Ethernet                   | | VCC1V0     | VCC5V0             | Buck              | IC25            | 1.0V +-5%                | 2.1A             | FPGA, Ethernet                   |
 | VCC1V35    | VCC5V0             | Buck              | IC25            | 1.35V +-5%               | 1.2A             | FPGA, DDR3                       | | VCC1V35    | VCC5V0             | Buck              | IC25            | 1.35V +-5%               | 1.2A             | FPGA, DDR3                       |
-| VCC1V8     | VCC5V0             | Buck              | IC25            | 1.8V +-10%               | 0.6A             | FPGA, Ethernet, USB              | +| VCC1V8     | VCC5V0             | Buck              | IC25            | 1.8V +-10%               | 0.6A             | FPGA                             | 
-| XADC_1V8   | VCC5V0             | LDO               | IC25            | 1.8V +-10%              | 0.1A             | FPGA XADC                        |+| VCC1V8_IO  | VCC1V8             | Load switch       | IC29            | 1.8V +-10%               | 0.6A             | Ethernet, USB                    | 
 +| XADC_1V8   | VCC5V0             | LDO               | IC25            | 1.8V +-10%               | 0.1A             | FPGA XADC                        |
 | XADC_1V25  | VCC3V3             | LDO               | IC27            | 1.25V +-0.12%            | 5mA              | FPGA XADC reference              | | XADC_1V25  | VCC3V3             | LDO               | IC27            | 1.25V +-0.12%            | 5mA              | FPGA XADC reference              |
-| ANA3V3     | VCC5V0             | LDO               | IC5             | 3.3V +-10%              | 0.1A             | Analog audio supply              | +| ANA3V3     | VCC5V0             | LDO               | IC5             | 3.3V +-10%               | 0.1A             | Analog audio supply              |
- +
-//Table 1.2.1. Zybo Z7 Power Rail Specifications//+
  
 ==== 1.3 Power Sequencing ==== ==== 1.3 Power Sequencing ====
  
-Input power to the board is gated by the TPS25940, a protection circuit providing both inrush and general current limit, over-voltage protection and current sense. Inrush current is limited by a ~4ms soft-start time.+Input power to the board is gated by the TPS25940, a protection circuit providing both inrush and general current limit, over-voltage protection, and current sense. Inrush current is limited by a ~4ms soft-start time.
  
-The supply rails downstream are daisy-chained to follow the Xilinx-recommended start-up sequence. Flicking the power switch (SW4) will enable the 1.0V rail, which enables the 1.8V digital supply rail, which in turn enables the I/O supply rails 3.3V and 1.35V. The 1.25V reference and 1.8V analog supply ramp together with the 3.3V rail. Once all the channels of the ADP5052 (IC25) supply reach regulation, the PGOOD signal will assert, enabling the 3.3V audio supply, lighting up the power LED (LD13), and de-asserting the Power-On Reset signal (PS_POR_B) of the Zynq.+The supply rails downstream are daisy-chained to follow the Xilinx-recommended start-up sequence. Flicking the power switch (SW4) will enable the 1.0V rail, which enables the 1.8V digital supply rail, which in turn enables the I/O supply rails 3.3V and 1.35V. The 1.25V reference and 1.8V analog supply ramp together with the 3.3V rail. Once all the channels of the ADP5052 (IC25) supply reach regulation, the PGOOD signal will assert, enabling the 3.3V audio supply and 1.8V I/O power rail, lighting up the power LED (LD13), and de-asserting the Power-On Reset signal (PS_POR_B) of the Zynq.
  
-Each power supply uses a soft-start ramp of 1-10ms to limit in-rush current. There is an additional delay of at least 130ms after the power rails reach regulation and before the Power-On Reset signal de-assert to allow for the PS_CLK (IC22) to stabilize. +Each power supply uses a soft-start ramp of 1-10ms to limit in-rush current. There is an additional delay of at least 130ms after the power rails reach regulation and before the Power-On Reset signal de-assert to allow for the PS_CLK (IC22) to stabilize. Further delay, typically 120 ms, is added before the deassert of the Zynq Power-On Reset to ensure that the Ethernet PHY, powered by the VCC1V8_IO rail and internally regulated, is ready before Zynq projects (without boot optimization) finish booting.
  
 ==== 1.4 Current Monitoring ==== ==== 1.4 Current Monitoring ====
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 //Figure 1.4.1. Current Consumption Equation// //Figure 1.4.1. Current Consumption Equation//
 +
 +----
 +==== Note: Sequencing Changes from Revision D.0 ====
 +
 +The power supply circuitry is slightly different depending on the revision of your board. Changes were introduced in Revision D.0 to conform to sequencing requirements imposed by the switch from the RTL8211E to the RTL28211F Ethernet PHY. Of particular note is the addition of a load switch separating all I/O circuitry connected to Zynq bank 501 (Ethernet, USB, UART, SD) from the main 1.8 V board supply. These changes mean that board power-on now takes more time. The dropdown below contains the power circuit overview diagram for revisions prior to D.0:
 +
 +--> Power Circuit Overview - Revision < D.0 #
 +{{ :reference:programmable-logic:zybo-z7:zybo-z7-power.png?700 |}}
 +<--
  
 ---- ----
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 **Stage 2**  **Stage 2** 
  
-The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple “Hello World” design, to a Second Stage Boot loader used to boot an operating system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple “Hello World” design, to a Second Stage Boot loader used to boot an operating system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
  
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 Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specific to the Zybo Z7 memory interface PCB design.  Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specific to the Zybo Z7 memory interface PCB design. 
  
-For more details on memory controller operation, refer to the Xilinx [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+For more details on memory controller operation, refer to the Xilinx [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
 ---- ----
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 ===== 4 Quad-SPI Flash ===== ===== 4 Quad-SPI Flash =====
  
-The Zybo Z7 features a Spansion S25FL128S 4-bit Quad-SPI serial NOR flash. The key device attributes are:  +The Zybo Z7 features a Flash memory used to provide non-volatile code and data storage. The key device attributes are:
-  * Part number S25FL128S +
   * 16 MiB (16,777,216 bytes)   * 16 MiB (16,777,216 bytes)
   * 1-bit, 2-bit, and 4-bit bus widths supported    * 1-bit, 2-bit, and 4-bit bus widths supported 
   * General use clock speeds up to 100 MHz, translating to 400 Mbps in Quad-SPI mode   * General use clock speeds up to 100 MHz, translating to 400 Mbps in Quad-SPI mode
-  * Zynq configuration clock speeds up to 94 MHz.+  * Zynq configuration clock speeds up to 94 MHz
   * Powered from 3.3V    * Powered from 3.3V 
  
-The Flash memory is used to provide non-volatile code and data storage. It can be used to initialize the PS and PL of the Zynq device with a Zynq Boot Image (also known as BOOT.BIN) generated using Xilinx tools such as Petalinux or Xilinx SDK. For information on booting the Zybo Z7 with a Zynq Boot image, see section "2.2 Quad SPI Boot Mode".+The Flash can be used to initialize the PS and PL of the Zynq device with a Zynq Boot Image (also known as BOOT.BIN) generated using Xilinx tools such as Petalinux or Xilinx SDK. For information on booting the Zybo Z7 with a Zynq Boot image, see section "2.2 Quad SPI Boot Mode".
  
 The Flash is also commonly used to store non-configuration data needed by the application. If doing this from a bare-metal application, The flash memory can be freely accessed using standalone libraries included with a Xilinx SDK BSP project. If doing this from a Petalinux generated embedded Linux system, the Flash can be partitioned as desired and mounted/accessed like a standard MTD block device. See the Petalinux and Xilinx SDK documentation for more information. The Flash is also commonly used to store non-configuration data needed by the application. If doing this from a bare-metal application, The flash memory can be freely accessed using standalone libraries included with a Xilinx SDK BSP project. If doing this from a Petalinux generated embedded Linux system, the Flash can be partitioned as desired and mounted/accessed like a standard MTD block device. See the Petalinux and Xilinx SDK documentation for more information.
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 The Flash connects to the Quad-SPI Flash controller of the Zynq-7000 PS via pins in MIO Bank 0/500 (specifically MIO[1:6,8]), as outlined in the Zynq Technical Reference Manual. Quad-SPI feedback mode is used, thus qspi_sclk_fb_out/MIO[8] is left to freely toggle and is connected only to a 20K pull-up resistor to 3.3V. This allows a Quad-SPI clock frequency greater than FQSPICLK2. The details of these connections do not need to be known when using the Zybo Z7 Vivado Board files, as they will automatically configure your project to work correctly with the on-board Flash. The Flash connects to the Quad-SPI Flash controller of the Zynq-7000 PS via pins in MIO Bank 0/500 (specifically MIO[1:6,8]), as outlined in the Zynq Technical Reference Manual. Quad-SPI feedback mode is used, thus qspi_sclk_fb_out/MIO[8] is left to freely toggle and is connected only to a 20K pull-up resistor to 3.3V. This allows a Quad-SPI clock frequency greater than FQSPICLK2. The details of these connections do not need to be known when using the Zybo Z7 Vivado Board files, as they will automatically configure your project to work correctly with the on-board Flash.
  
-A globally unique MAC address is programmed into the One-Time-Programmable (OTP) region of the Flash on each Zybo Z7 at the factory. For more information on this, see section "10 Ethernet".+A globally unique MAC address is programmed into each Zybo Z7's flash at the factory. For more information on this, see section "10 Ethernet".
  
-The OTP region also includes a factory-programmed read-only 128-bit random number. The very lowest address range [0x00;0x0F] can be read to access the random number. See the Spansion S25FL128S datasheet for information on this random number and accessing the OTP region.+One of several memory parts may be loaded on your board, depending on the revision of the board. To find out which part is loaded, check the PCB revision on the underside of the PCB. The table below lists the possible load options: 
 + 
 +//Table 4.1. Flash part memory loaded// 
 +^ Manufacturer  ^ P/N                                ^ PCB Revision  ^ 
 +| Spansion      | S25FL128SAGMFI00                   | < D.0         | 
 +| Winbond       | <nowiki>W25Q128JV[S|P]xM</nowiki>  | ≥ D.0         | 
 + 
 +The two part numbers are highly compatible, however, the W25Q128JV is not functionally equivalent to the S25FL128S and might require changes to customer applications (embedded software) depending on the board support package in use (OS, drivers, and libraries). It might be possible to implement any changes that might be needed in such a way to keep compatibility with all load options. A non-exhaustive list of the differences between the W25Q128JV and the S25FL128S: 
 + 
 +  * Manufacturer & Device ID: “EFh 70h 18h” vs. “01h 20h 18h” 
 +  * 3x256-B Security Registers vs. 32x32-B OTP Array 
 +  * Security Register Read command 48h vs. OTP Read command 4Bh 
 +  * Memory organization: 256 64KB or 4096 4KB uniform erase sectors vs. 32 4-KB bottom and 256 64-KB hybrid erase sectors 
 +  * For revisions prior to D.0, the OTP region also includes a factory-programmed read-only 128-bit random number. The very lowest address range [0x00;0x0F] can be read to access the random number. See the Spansion S25FL128S datasheet for information on this random number and accessing the OTP region. The W25Q128JV's Security Registers do not have this random number. 
 +  * Maximum clock frequency for QPP, 4QPP commands: 133 MHz vs. 80MHz. 
 + 
 +Embedded software work-arounds depending on the board support package: 
 + 
 +  * Stand-alone environments should be modified if special non-standard commands are in use. For example, OTP read/write features should account for opcode and address changes. Standard flash array read and write commands, single or quad are compatible between the two. 
 +  * The MAC address for the Gigabit Ethernet port needs to be read out using the Read Security Registers (48h) command and the address range [001000h;001005h]. The byte order is the same as before, ie. the first byte in transmission byte order is at the lowest address. 
 +  * Xilinx tools such as Vitis and Vivado support the W25Q128JV once the correct part number is chosen when targeting the Flash memory. Choose the “w25q128fv-qspi-x4-single” option which is an alias for the “w25q128jv-qspi-x4-single”. Support for w25q128jv is available in version 2018.3 and above. 
 +  * U-boot and Linux kernel built using the “jedec,spi-nor” compatibility string for the flash node needs no changes, as the part is identified during probe. If the old way of specifying a fixed part is used, it is recommended that the compatibility string is replaced with “jedec,spi-nor”. 
 + 
 +**Note:** //Refer to the manufacturers' datasheets[([[https://www.infineon.com/dgdl/Infineon-S25FL128S_S25FL256S_128_Mb_(16_MB)_256_Mb_(32_MB)_3.0V_SPI_Flash_Memory-DataSheet-v18_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecfb6a64a17|S25FL128S Datasheet]])][([[https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.pdf|W25Q128JV Datasheet]])] and Zynq Technical Reference Manual[([[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Xilinx Zynq Technical Reference Manual (UG585)]])] for more information.// 
 + 
 +~~REFNOTES~~
  
 ---- ----
Line 423: Line 457:
 ===== 8 microSD Slot ===== ===== 8 microSD Slot =====
  
-The Zybo Z7 provides a microSD slot (J4) for non-volatile external memory storage as well as booting the Zynq. The slot is wired to Bank 1/501 MIO[40-45], and also includes a card detect signal attached to MIO 47. On the PS side peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 8.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference Manual]], SDIO host mode is the only mode supported.+The Zybo Z7 provides a microSD slot (J4) for non-volatile external memory storage as well as booting the Zynq. The slot is wired to Bank 1/501 MIO[40-45], and also includes a card detect signal attached to MIO 47. On the PS side peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 8.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference Manual]], SDIO host mode is the only mode supported.
  
 | **Signal Name**  | **Description**  | **Zynq Pin**  | **SD Slot Pin**  | | **Signal Name**  | **Description**  | **Zynq Pin**  | **SD Slot Pin**  |
Line 462: Line 496:
 ===== 10 Ethernet ===== ===== 10 Ethernet =====
  
-The Zybo Z7 uses a Realtek RTL8211E-VL PHY to implement a 10/100/1000 Ethernet port for network connection. The PHY connects to MIO Bank 501 (1.8V) and interfaces to the Zynq-7000 AP SoC via RGMII for data and MDIO for management. The auxiliary interrupt (INTB) and reset (PHYRSTB) signals connect to PL pins to be accessed via EMIO. The connection diagram can be seen on Figure 10.1.+The Zybo Z7 uses a Realtek PHY to implement a 10/100/1000 Ethernet port for network connection. 
 + 
 +One of several Realtek PHY parts may be loaded on your board, depending on the revision of the board. To find out which part is loaded, check the PCB revision on the underside of the PCB. These devices are not functionally equivalent and may require changes to user applications, depending on the board support package (OS, drivers, and libraries) used. The table below lists the possible load options, and a non-exhaustive list of the differences between these two PHY devices is presented at the end of this section.  
 + 
 +//Table 10.1: Ethernet PHY part loaded// 
 +^ P/N       ^ PCB Revision  ^ 
 +| RTL8211E  | < D.0         | 
 +| RTL8211F  | ≥ D.0         | 
 + 
 +The PHY connects to MIO Bank 501 (1.8V) and interfaces to the Zynq-7000 AP SoC via RGMII for data and MDIO for management. The auxiliary interrupt (INTB) and reset (PHYRSTB) signals connect to PL pins to be accessed via EMIO. The connection diagram can be seen on Figure 10.1.
  
 After power-up the PHY starts with Auto Negotiation enabled, advertising 10/100/1000 link speeds and full duplex. If there is an Ethernet-capable partner connected, the PHY automatically establishes a link with it, even with the Zynq not configured. After power-up the PHY starts with Auto Negotiation enabled, advertising 10/100/1000 link speeds and full duplex. If there is an Ethernet-capable partner connected, the PHY automatically establishes a link with it, even with the Zynq not configured.
  
-{{ :reference:programmable-logic:zybo-z7:zybo-z7-eth.png?600 |}}+{{ :programmable-logic:zybo-z7:zybo-z7-eth-d0.png?600 |}}
  
 //Figure 10.1. Ethernet PHY signals// //Figure 10.1. Ethernet PHY signals//
  
-Two status indicator LEDs are on-board near the RJ-45 connector that indicate traffic (LD8) and valid link state (LD7). Table 10.1 shows the default behavior.+Three status indicator LEDs, labeled "10", "100", and "1G" near the RJ-45 connector indicate both status and link state of the three connection speeds. Table 10.1 shows the default behavior. 
 + 
 +|  **Designator**  |  **State**  |  **Description**           | 
 +|  10              | Steady on   | Link Up at 10 Mbps         | 
 +| :::              | Blinking    | Transmitting or Receiving  | 
 +|  100             | Steady on   | Link Up at 100 Mbps        | 
 +| :::              | Blinking    | Transmitting or Receiving  | 
 +|  1G              | Steady on   | Link Up at 1000 Mbps       | 
 +| :::              | Blinking    | Transmitting or Receiving  | 
 + 
 +//Table 10.1. Ethernet status LEDs// 
 + 
 +Prior to revision D.0, only two status indicator LEDs were used ("LINK" and "ACT"). Check the dropdown below to determine their behavior. 
 + 
 +--> Revision < D.0 LED Behavior #
  
 |  **Function**  |  **Designator**  |  **State**                |  **Description**                            | |  **Function**  |  **Designator**  |  **State**                |  **Description**                            |
Line 477: Line 534:
 |  ACT           |  LD8             | Blinking                  | Transmitting or Receiving                   | |  ACT           |  LD8             | Blinking                  | Transmitting or Receiving                   |
  
- +<--
-//Table 10.1. Ethernet status LEDs//+
  
 The Zynq incorporates two independent Gigabit Ethernet Controllers. They implement a 10/100/1000 half/full duplex Ethernet MAC. Of these two, GEM 0 can be mapped to the MIO pins where the PHY interfaces. Since the MIO bank is powered from 1.8V, the RGMII interface uses 1.8V HSTL Class 1 drivers. For this I/O standard an external reference of 0.9V is provided in bank 501 (PS_MIO_VREF). Mapping out the correct pins and configuring the interface is handled by the Zybo Z7 Vivado board files. The Zynq incorporates two independent Gigabit Ethernet Controllers. They implement a 10/100/1000 half/full duplex Ethernet MAC. Of these two, GEM 0 can be mapped to the MIO pins where the PHY interfaces. Since the MIO bank is powered from 1.8V, the RGMII interface uses 1.8V HSTL Class 1 drivers. For this I/O standard an external reference of 0.9V is provided in bank 501 (PS_MIO_VREF). Mapping out the correct pins and configuring the interface is handled by the Zybo Z7 Vivado board files.
  
-Although the default power-up configuration of the PHY might be enough in most applications, the MDIO bus is available for management. The RTL8211E-VL is assigned the 5-bit address 00001 on the MDIO bus. With simple register read and write commands, status information can be read out or configuration changed. The Realtek PHY follows industry-standard register map for basic configuration.+Although the default power-up configuration of the PHY might be enough in most applications, the MDIO bus is available for management. The PHY is assigned the 5-bit address 00001 on the MDIO bus. With simple register read and write commands, status information can be read out or configuration changed. The Realtek PHY follows industry-standard register map for basic configuration.
  
-The RGMII specification calls for the receive (RXC) and transmit clock (TXC) to be delayed relative to the data signals (RXD[0:3], RXCTL and TXD[0:3], TXCTL). Xilinx PCB guidelines also require this delay to be added. The RTL8211E-VL is capable of inserting a 2ns delay on both the TXC and RXC so that board traces do not need to be made longer.+The RGMII specification calls for the receive (RXC) and transmit clock (TXC) to be delayed relative to the data signals (RXD[0:3], RXCTL and TXD[0:3], TXCTL). Xilinx PCB guidelines also require this delay to be added. The PHY is capable of inserting a 2ns delay on both the TXC and RXC so that board traces do not need to be made longer.
  
-On an Ethernet network each node needs a unique MAC address. To this end, the one-time-programmable (OTP) region of the Quad-SPI flash has been programmed at the factory with a 48-bit globally unique EUI-48/64™ compatible identifier. The OTP address range [0x20;0x25] contains the identifier with the first byte in transmission byte order being at the lowest address. Refer to the [[http://www.cypress.com/file/177966/download|Flash memory datasheet]] for information on how to access the OTP regions. When using Petalinux, this is automatically handled in the U-boot boot-loader, and the Linux system is automatically configured to use this unique MAC address. The identifier is also printed on a sticker found on the top-side of the Zybo Z7 right next to the mode jumper (JP5) and above the headphone output jack. +On an Ethernet network each node needs a unique MAC address. The Quad-SPI flash memory is programmed with a 48-bit globally unique EUI-48/64™ compatible identifier during manufacturing. Due to changes in which flash part is loaded on the Zybo Z7, accessing the MAC address differs slightly depending on which revision of the board you have. For revisions prior to D.0, the MAC address is contained in the one-time-programmable (OTP) region of the Quad-SPI flash. The OTP address range [0x20;0x25] contains the identifier with the first byte in transmission byte order being at the lowest address. For revisions after and including D.0, the MAC address is contained in the scurity registers, and needs to be read out using the Read Security Registers (48h) command from the address range [001000h;001005h]. The byte order is the same as in older revisions, ie. the first byte in transmission byte order is at the lowest address. Refer to the datasheet for the flash  
 + 
 +When using Petalinux, regardless of which flash memory is loaded, reading the MAC address is automatically handled in the U-boot boot-loader, and the Linux system is automatically configured to use this unique MAC address. The identifier is also printed on a sticker found on the top-side of the Zybo Z7 right next to the mode jumper (JP5) and above the headphone output jack. 
  
 For getting started using the ethernet port in a bare-metal application, Xilinx provides a lwip TCP/IP stack that can be automatically generated in Xilinx SDK along with an echo server example. When using the Zybo Z7 with a Petalinux generated embedded Linux system, the ethernet port will automatically appear as a network device typically named eth0. See the Petalinux and Xilinx SDK documentation for more information. For getting started using the ethernet port in a bare-metal application, Xilinx provides a lwip TCP/IP stack that can be automatically generated in Xilinx SDK along with an echo server example. When using the Zybo Z7 with a Petalinux generated embedded Linux system, the ethernet port will automatically appear as a network device typically named eth0. See the Petalinux and Xilinx SDK documentation for more information.
  
 For more low-level information on using the Zynq-7000 Gigabit Ethernet MAC, refer to the Xilinx Zynq Technical Reference Manual. For more low-level information on using the Zynq-7000 Gigabit Ethernet MAC, refer to the Xilinx Zynq Technical Reference Manual.
 +
 +----
 +
 +Differences between the RTL8211E and RTL8211F:
 +
 +  * PHYSR1 (PHY Specific Status Register 1) at Page 0xA43, Address 0x1A vs. PHYSR at Address 0x11. Register field layout also differs. Affected functionality includes auto-negotiated speed, duplex and link detection.
 +  * INSR (Interrupt Status Register) at Page 0xA43, Address 0x1D vs. INSR at Address 0x13. Register field layout also differs. Affected functionality is interrupt detection.
 +  * INER (Interrupt Enable Register) power-on defaults to only the PHY Register Accessible Interrupt being enabled vs. all interrupt sources enabled. Interrupt sources must now be explicitly enabled, if required.
 +  * Power-on sequencing requirements changed. The RTL8211F now regulates its own core voltage, as its internal regulator cannot be turned off. The 1.8V I/O voltage sequencing requirements forced all I/O circuitry in bank 501 (Ethernet, USB, UART, SD) to be separated from the main 1.8V board supply by a load switch. This I/O supply is now the last in the sequence to power-on. The board power-on reset circuitry required to be changed as well. Power-on now takes more time.
 +  * Power-on core logic ready time 100 ms vs. 20 ms. The RTL8211F reserves a 100 ms window after power-on that is not being used for now. The only register access allowed in this window is Page 0xa46, Reg. 20, bit[1]=1 (PHY Special Config Done), to skip this window and enter normal operating state. Otherwise, the PHY will do it automatically when the wait period ends. Entering normal operating state is signaled by the ETH_INT_B interrupt. This behavior affects only very short boot time applications, which have been explicitly optimized for this purpose. Such applications must make sure they monitor the PHY interrupt and do not access any registers other than the one stated above before the Special Config Done even arrives. The typical boot time of a small non-optimized stand-alone application from the QSPI flash is 86 ms from the de-assertion the PS_POR_B signal. The PS_POR_B delay was increased and the PHY is now taken out of reset ahead of the Zynq. Therefore, without specific boot time optimizations, the RTL8211F is guaranteed to be ready by the time the software needs it.
 +  * Three PHY status LEDs vs. two. The Link and Activity LEDs have been replaced by one LED for each link speed that integrate link and activity. These are now labeled “10”, “100”, and “1G”.
 +
 +----
 +
 +Suggested embedded software work-arounds depending on the board support package:
 +
 +  * Stand-alone environments are expected to be using Xilinx’s lwip library with built-in PHY support for the RTL8211E. This will need to be replaced by a modified library that adds support for the RTL8211F. The patched library is published on Digilent’s Github page: [[https://github.com/Digilent/embeddedsw/tree/realtek-21.1|Patched Library]]. It is expected to be upstreamed to Xilinx in a future Vitis version. \\ If the ETH_INT_B interrupt is used in the application, the necessary interrupt sources must now be enabled explicitly. \\ If the application optimizes boot time, the PHY needs to be initialized by writing Page 0xa46, Reg. 20, bit[1]=1 (PHY Special Config Done).
 +  * U-boot and Linux kernel built using Petalinux 2016.1 or later support RTL8211F with no changes necessary.
  
 ---- ----
Line 616: Line 692:
 The fan connector is not loaded on the Zybo Z7-10 because additional cooling is typically not needed with the fewer available FPGA resources. The fan connector is not loaded on the Zybo Z7-10 because additional cooling is typically not needed with the fewer available FPGA resources.
  
-Digilent recommends two different fan choices for the Zybo Z7-20: A Sunon MC17080V2-0000-A99 or a Sunon MF17080V2-1000G99. +Digilent recommends several different fan choices for the Zybo Z7-20: A Sunon MC17080V2-0000-A99, Sunon MF17080V2-10000-G99, or a Sunon MF17080V1-10000-G99.  
 + 
 +---- 
 + 
 +The [[https://digilent.com/shop/zybo-z7-20-fan-kit/|Zybo Z7-20 Fan Kit]] ships with either the Sunon MF17080V2-10000-G99 or Sunon MF17080V1-10000-G99 fan. 
 + 
 +These fans are not functionally equivalent and might require changes to customer applications (embedded software). 
 + 
 +The main differences between the MF17080V1-10000-G99 and the MF17080V2-10000-G99: 
 + 
 +  * 21000 RPM vs. 16500 RPM +-15%, 
 +  * 21.5 dB vs 14.2 dB acoustic noise, 
 +  * Max 107 mA vs. 76 mA current consumption, 
 +  * Lower minimum voltage 2.8V vs. 3.3V. 
 + 
 +Embedded software might need changes to accommodate the higher rotation speed if the speed is measured via the feedback signal. The higher power consumption is expected not to be a concern since the fan kit is expected to be used in high-powered designs with an external barrel jack supply with reserve power available.
  
 ---- ----
Line 660: Line 751:
 //Figure 15.2. Attaching a Pcam// //Figure 15.2. Attaching a Pcam//
  
-The MIPI CSI-2 bus is passively terminated on the Zybo Z7 and connected directly to the Zynq PL. The guidelines described in Xilinx application note [[https://www.xilinx.com/support/documentation/application_notes/xapp894-d-phy-solutions.pdf| XAPP894 D-PHY solutions]] were followed in order to implement a compatible D-PHY receiver using the Zynq. The interface is tested to operate at up to 672 Mbps on each lane. Speeds up to 950 Mbps on each lane are possible based on the Zynq-7000 timing specifications, however they are not validated on the Zybo Z7.+The MIPI CSI-2 bus is passively terminated on the Zybo Z7 and connected directly to the Zynq PL. The guidelines described in Xilinx application note [[https://docs.xilinx.com/v/u/en-US/xapp894-d-phy-solutions| XAPP894 D-PHY solutions]] were followed in order to implement a compatible D-PHY receiver using the Zynq. The interface is tested to operate at up to 672 Mbps on each lane. Speeds up to 950 Mbps on each lane are possible based on the Zynq-7000 timing specifications, however they are not validated on the Zybo Z7.
  
 A [[https://www.xilinx.com/products/intellectual-property/ef-di-mipi-csi-rx.html|MIPI CSI-2 Receiver IP core]] is available from Xilinx, and includes embedded Linux support. It requires a license in order to use, however it is possible to obtain an evaluation license from Xilinx for free. A [[https://www.xilinx.com/products/intellectual-property/ef-di-mipi-csi-rx.html|MIPI CSI-2 Receiver IP core]] is available from Xilinx, and includes embedded Linux support. It requires a license in order to use, however it is possible to obtain an evaluation license from Xilinx for free.
Line 730: Line 821:
 Although we strive to provide perfect products, we are not infallible. The Zybo Z7 is subject to the limitations below. Although we strive to provide perfect products, we are not infallible. The Zybo Z7 is subject to the limitations below.
 ^ Product Name  ^ Variant  ^ Revision  ^ Problem                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ^ Status        ^ ^ Product Name  ^ Variant  ^ Revision  ^ Problem                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ^ Status        ^
-| Zybo Z7       | All      | All       | Negative CK-to-DQS delays in the board files are causing critical warnings in Vivado >2017.4:\\ [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values. \\ \\ The negative values are due to CK trace being shorter than any of the four DQS traces.\\ \\ In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Zybo (Z7) was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Zybo (Z7)s shipped to customers are functionally tested and pass the DDR3 calibration process. \\ \\ Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: https://www.xilinx.com/support/answers/53039.html. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. \\ \\ To silence the warnings, zero board delays can be set in Processing System configuration. The calibration algorithm seems to be using zero starting values anyway when negative delays are given.  | will not fix  |+| Zybo Z7       | All      | All       | Negative CK-to-DQS delays in the board files are causing critical warnings in Vivado >2017.4:\\ [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values. \\ \\ The negative values are due to CK trace being shorter than any of the four DQS traces.\\ \\ In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Zybo (Z7) was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Zybo (Z7)s shipped to customers are functionally tested and pass the DDR3 calibration process. \\ \\ Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: [[https://support.xilinx.com/s/article/53039]]. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. \\ \\ To silence the warnings, zero board delays can be set in Processing System configuration. The calibration algorithm seems to be using zero starting values anyway when negative delays are given.  | will not fix  |
 {{tag>rm doc zybo-z7}} {{tag>rm doc zybo-z7}}