Zybo Z7 DMA Audio Demo

This demo contains a Vivado IP Integrator project and Vitis projects that control the Zybo Z7's audio codec in order to record and play back audio

The audio demo records a 5 second sample from microphone(J6) or line in (J7) and plays it back on headphone out (J5). Recording and playback are started by push buttons. Messages are printed to a connected serial terminal that provide information on the status of the application.

Additional information on how this demo can be used can be found in appropriate READMEs, linked below.

• Zybo Z7 with a MicroUSB Programming Cable
• Vivado and Vitis installations compatible with the latest release of this demo (2020.1)
  • See Installing Vivado, Vitis, and Digilent Board Files for installation instructions.
• Serial Terminal application to receive messages printed by the demo
  • See Installing and Using a Terminal Emulator (Redirect) for more information.
• Headphones or Speakers
• Audio Input Device - such as a microphone or computer with 3.5mm audio jack, etc

First and foremost, releases - consisting of a set of files for download - are only compatible with a specific version of the Xilinx tools, as specified in the name of the release (referred to as a release tag). In addition, releases are only compatible with the specified variant of the board. For example, a release tagged “20/DMA/2020.1” for the Zybo Z7 is only to be used with the -20 variant of the board and Xilinx tools (Vivado and Vitis) version 2020.1.

The latest release version for this demo is highlighted in green.

Note: Releases for FPGA demos from before 2020.1 used a different git structure, and used a different release tag naming scheme.

Note for Advanced Users: All demos for the Zybo Z7 are provided through the Zybo-Z7 repository on Github. Further documentation on the structure of this repository can be found on this wiki's Digilent FPGA Demo Git Repositories (Redirect) page.

Instructions on the use of the latest release can be found in this dropdown:

Using the Latest Release

This page has been moved, the new location is Using a Digilent FPGA Github Demo's Releases (2020.1).

Set up the Zybo Z7

Plug the Zybo Z7 into the computer via the microUSB programming cable.

Plug in your microphone or aux input into the appropriate jack on your Zybo (MIC IN or LINE IN, respectively). Plug your speakers/headphones into the headphone jack (HPH OUT).

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This page has been moved, the new location is Using a Digilent FPGA Github Demo's Releases (2020.1).

At this point, the demo is now running on your board. Refer to the Description section of this document for more information on what it does.

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Additional steps beyond here present how you can use the other archive provided in the release, containing the hardware project, to rebuild the Vivado project, and use a newly exported XSA file to update the platform in Vitis.

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This page has been moved, the new location is Using a Digilent FPGA Github Demo's Releases (2020.1).

Audio playback and recording are controlled by push buttons as below.

To record from MIC IN, press BTN1. To record from LINE IN, press BTN3. Once the recording is activated, the message “Start Recording…” will be sent over UART and the demo will record 5 seconds of audio. If any buttons are pressed during the recording, the message “Still Recording…” will be sent over UART.

To play to HPH OUT, press BTN2. Once the playback is activated, the message “Start Playback…” will be sent over UART and the demo will play 5 seconds of audio. If any buttons are pressed during the playback, the message “Still Playing…” will be sent over UART.

All materials related to the use of the Zybo Z7 can be found on its Resource Center.

For a walkthrough of the process of creating a simple baremetal software project in Vivado and Vitis, see Getting Started with Vivado IP Integrator and Vitis (Redirect). Information on important parts of the GUIs, and indirect discussion of the steps required to modify, rebuild, and run this demo in hardware can also be found here.

For technical support, please visit the FPGA section of the Digilent Forum.

{{tag>project zybo-z7}}