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programmable-logic:usb104a7:reference-manual [2021/05/14 16:07] – ↷ Links adapted because of a move operation Arthur Brownprogrammable-logic:usb104a7:reference-manual [2022/10/04 04:38] (current) – external edit 127.0.0.1
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 === 6.1. DPTI Parallel Data Transfer Interface === === 6.1. DPTI Parallel Data Transfer Interface ===
  
-The DPTI interface is an 8-bit wide parallel FIFO-style data interface supporting both asynchronous and synchronous modes. In FTDI terminology, DPTI is equivalent to "FT245-style Asynchronous or Synchronous FIFO Interface". It is available in both synchronous and asynchronous modes, configurable from the DPTI API. In synchronous mode, data transfer is timed by the clock provided by the USB controller (connected to the FPGA on pin P17). In asynchronous mode, data transfer occurs on transitions of the read and write control signals. THe USB controller emulates a FIFO memory, providing status signals about the availability of data to be read and free space for data to be written. The FPGA controls data transfer through read, write, and output enable signals. Data transfer speeds of up to 40 MB/s are supported in synchronous mode. This interface is summarized in Figure 6.1.1, below:+The DPTI interface is an 8-bit wide parallel FIFO-style data interface supporting both asynchronous and synchronous modes. In FTDI terminology, DPTI is equivalent to "FT245-style Asynchronous or Synchronous FIFO Interface". It is available in both synchronous and asynchronous modes, configurable from the DPTI API. In synchronous mode, data transfer is timed by the clock provided by the USB controller (connected to the FPGA on pin P17). In asynchronous mode, data transfer occurs on transitions of the read and write control signals. The USB controller emulates a FIFO memory, providing status signals about the availability of data to be read and free space for data to be written. The FPGA controls data transfer through read, write, and output enable signals. Data transfer speeds of up to 40 MB/s are supported in synchronous mode. This interface is summarized in Figure 6.1.1, below:
  
 {{ :reference:programmable-logic:usb104a7:usb104a7-dpti.png?nolink&600 |}} {{ :reference:programmable-logic:usb104a7:usb104a7-dpti.png?nolink&600 |}}