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programmable-logic:sword:reference-manual [2021/05/14 23:06] – ↷ Links adapted because of a move operation Arthur Brownprogrammable-logic:sword:reference-manual [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 The Sword board's Kintex-7 XC7K325T FPGA is compatible with Xilinx’s high-performance Vivado® Design Suite and requires the full software license. The Sword board's Kintex-7 XC7K325T FPGA is compatible with Xilinx’s high-performance Vivado® Design Suite and requires the full software license.
-WebPack is not supported. Licensing information for Vivado can be found [[http://www.xilinx.com/products/design-tools/vivado.html|here]]. Academic institutes can request full Vivado licenses [[http://www.xilinx.com/support/university/donation-program.html|here]].+WebPack is not supported. Licensing information for Vivado can be found [[https://www.xilinx.com/products/design-tools/vivado.html|here]]. Academic institutes can request full Vivado licenses [[https://www.xilinx.com/support/university/donation-program.html|here]].
  
  
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 For clocking, it is recommended that the System clock be set to “Differential”, and connected directly to the onboard 200MHz oscillator on pins AD12 and AD11 (P and N respectively). No reference clock is required. For clocking, it is recommended that the System clock be set to “Differential”, and connected directly to the onboard 200MHz oscillator on pins AD12 and AD11 (P and N respectively). No reference clock is required.
  
-The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For those using the MIG with a MicroBlaze project, the Sword MIG settings and pinout will be automatically imported from the [[https://reference.digilentinc.com/reference/software/vivado/board-files|Digilent Vivado board files]].+The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For those using the MIG with a MicroBlaze project, the Sword MIG settings and pinout will be automatically imported from the [[software/vivado/board-files|Digilent Vivado board files]].
  
-For more details on the Xilinx memory interface solutions refer to the 7 Series FPGAs Memory Interface Solutions [[http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_1/ug586_7Series_MIS.pdf|User Guide (ug586)]].+For more details on the Xilinx memory interface solutions refer to the 7 Series FPGAs Memory Interface Solutions [[https://docs.xilinx.com/v/u/2.1-English/ug586_7Series_MIS|User Guide (ug586)]].
  
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 ===== 7 Oscillators/Clocks ===== ===== 7 Oscillators/Clocks =====
  
-The Sword board includes several oscillators and crystals, of which one is connected to the FPGA. One differential LVDS 200MHz oscillator is connected to MRCC GPIO pins AD12/AD11 in bank 33. The clock can drive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. Some rules restrict which MMCMs and PLLs may be driven by the 200MHz input clock. For a full description of these rules and of the capabilities of the Kintex-7 clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” ([[http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf|ug472]]) available from Xilinx.+The Sword board includes several oscillators and crystals, of which one is connected to the FPGA. One differential LVDS 200MHz oscillator is connected to MRCC GPIO pins AD12/AD11 in bank 33. The clock can drive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. Some rules restrict which MMCMs and PLLs may be driven by the 200MHz input clock. For a full description of these rules and of the capabilities of the Kintex-7 clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” ([[https://docs.xilinx.com/v/u/en-US/ug472_7Series_Clocking|ug472]]) available from Xilinx.
  
 Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy-to-use wrapper component around these clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Vivado and IP Integrator tools. Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy-to-use wrapper component around these clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Vivado and IP Integrator tools.
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 //Table 22.1.1. Shield Voltage Specifications// //Table 22.1.1. Shield Voltage Specifications//
  
-For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://www.xilinx.com/support/documentation/data_sheets/ds182_kintex_7_data_sheet.pdf|Kintex-7 datasheet]] from Xilinx.+For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://docs.xilinx.com/v/u/en-US/ds182_Kintex_7_Data_Sheet|Kintex-7 datasheet]] from Xilinx.
  
 The pins on the shield connector typically used for I2C signals are labeled as SCL and SDA. When using these signals to implement an I2C bus it is necessary to attach a pull-up resistor to them. On the Sword, this can be done by placing two shorting blocks horizontally across the J4 header. The pins on the shield connector typically used for I2C signals are labeled as SCL and SDA. When using these signals to implement an I2C bus it is necessary to attach a pull-up resistor to them. On the Sword, this can be done by placing two shorting blocks horizontally across the J4 header.