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programmable-logic:sword:reference-manual [2021/05/14 16:04] – ↷ Page moved from reference:programmable-logic:sword:reference-manual to programmable-logic:sword:reference-manual Arthur Brownprogrammable-logic:sword:reference-manual [2022/10/04 04:38] (current) – external edit 127.0.0.1
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 The Sword board's Kintex-7 XC7K325T FPGA is compatible with Xilinx’s high-performance Vivado® Design Suite and requires the full software license. The Sword board's Kintex-7 XC7K325T FPGA is compatible with Xilinx’s high-performance Vivado® Design Suite and requires the full software license.
-WebPack is not supported. Licensing information for Vivado can be found [[http://www.xilinx.com/products/design-tools/vivado.html|here]]. Academic institutes can request full Vivado licenses [[http://www.xilinx.com/support/university/donation-program.html|here]].+WebPack is not supported. Licensing information for Vivado can be found [[https://www.xilinx.com/products/design-tools/vivado.html|here]]. Academic institutes can request full Vivado licenses [[https://www.xilinx.com/support/university/donation-program.html|here]].
  
  
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 For clocking, it is recommended that the System clock be set to “Differential”, and connected directly to the onboard 200MHz oscillator on pins AD12 and AD11 (P and N respectively). No reference clock is required. For clocking, it is recommended that the System clock be set to “Differential”, and connected directly to the onboard 200MHz oscillator on pins AD12 and AD11 (P and N respectively). No reference clock is required.
  
-The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For those using the MIG with a MicroBlaze project, the Sword MIG settings and pinout will be automatically imported from the [[https://reference.digilentinc.com/reference/software/vivado/board-files|Digilent Vivado board files]].+The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For those using the MIG with a MicroBlaze project, the Sword MIG settings and pinout will be automatically imported from the [[software/vivado/board-files|Digilent Vivado board files]].
  
-For more details on the Xilinx memory interface solutions refer to the 7 Series FPGAs Memory Interface Solutions [[http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_1/ug586_7Series_MIS.pdf|User Guide (ug586)]].+For more details on the Xilinx memory interface solutions refer to the 7 Series FPGAs Memory Interface Solutions [[https://docs.xilinx.com/v/u/2.1-English/ug586_7Series_MIS|User Guide (ug586)]].
  
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 The Sword board includes 6 MB of Static Random-Access Memory (SRAM). The SRAM is made up of two memories with a shared 20-bit address bus and separate control signals. SRAM1 has 16 bi-directional data signals and can contain up to 2MB of data. SRAM2 has 32 bi-directional data signals and can contain up to 4MB of data. The parts used to implement these memories are three CY7C1061GE30-10BVXI chips. Each of the three parts has a theoretical maximum data bandwidth of 100Mbps per data signal used. The Sword board includes 6 MB of Static Random-Access Memory (SRAM). The SRAM is made up of two memories with a shared 20-bit address bus and separate control signals. SRAM1 has 16 bi-directional data signals and can contain up to 2MB of data. SRAM2 has 32 bi-directional data signals and can contain up to 4MB of data. The parts used to implement these memories are three CY7C1061GE30-10BVXI chips. Each of the three parts has a theoretical maximum data bandwidth of 100Mbps per data signal used.
  
-The Xilinx AXI External Memory Controller (EMC) IP can be used to connect the SRAM memories to a Microblaze processor. At the time of writing, this is not supported in Digilent's board files, meaning that the SRAM interface pins must be manually constrained. For pin-mappings between the FPGA and SRAM, please see the Sword Master XDC available at the [[:reference:programmable-logic:sword:start|Sword Resource Center]]. See the datasheet for the [[http://www.cypress.com/file/46676/download|CY7C1061GE30 part]] for more information about the memories.+The Xilinx AXI External Memory Controller (EMC) IP can be used to connect the SRAM memories to a Microblaze processor. At the time of writing, this is not supported in Digilent's board files, meaning that the SRAM interface pins must be manually constrained. For pin-mappings between the FPGA and SRAM, please see the Sword Master XDC available at the [[programmable-logic:sword:start|Sword Resource Center]]. See the datasheet for the [[http://www.cypress.com/file/46676/download|CY7C1061GE30 part]] for more information about the memories.
  
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 The Parallel Flash consists of two Cypress devices (part number S29GL128S10DHI010) and is organized as 8 Mwords of 32bits each. The two devices share address signals and have separate control signals. They each contain 128 individually erasable 1 Mbit sectors. Several Address Space Overlays provide a variety of additional functions, including data protection, and access to the status register, device identification and common flash interface. The parallel flash offers 90 ns read cycle times, with 15 ns page-mode reads within blocks. Each device has an internal 512-byte write buffer that can be used to program the flash at an effective rate of 1.33us per word (typical). The Parallel Flash consists of two Cypress devices (part number S29GL128S10DHI010) and is organized as 8 Mwords of 32bits each. The two devices share address signals and have separate control signals. They each contain 128 individually erasable 1 Mbit sectors. Several Address Space Overlays provide a variety of additional functions, including data protection, and access to the status register, device identification and common flash interface. The parallel flash offers 90 ns read cycle times, with 15 ns page-mode reads within blocks. Each device has an internal 512-byte write buffer that can be used to program the flash at an effective rate of 1.33us per word (typical).
  
-The Xilinx AXI External Memory Controller (EMC) IP can be used to connect the Parallel Flash to a Microblaze processor. At the time of writing, this is not supported in Digilent's board files, meaning that the Flash interface pins must be manually constrained. For pin-mappings between the FPGA and Parallel Flash devices, please see the Sword Master XDC available at the [[:reference:programmable-logic:sword:start|Sword Resource Center]]. For more information about the memories, please see the [[http://www.cypress.com/file/177976/download|Cypress part datasheet]].+The Xilinx AXI External Memory Controller (EMC) IP can be used to connect the Parallel Flash to a Microblaze processor. At the time of writing, this is not supported in Digilent's board files, meaning that the Flash interface pins must be manually constrained. For pin-mappings between the FPGA and Parallel Flash devices, please see the Sword Master XDC available at the [[programmable-logic:sword:start|Sword Resource Center]]. For more information about the memories, please see the [[http://www.cypress.com/file/177976/download|Cypress part datasheet]].
  
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 ===== 7 Oscillators/Clocks ===== ===== 7 Oscillators/Clocks =====
  
-The Sword board includes several oscillators and crystals, of which one is connected to the FPGA. One differential LVDS 200MHz oscillator is connected to MRCC GPIO pins AD12/AD11 in bank 33. The clock can drive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. Some rules restrict which MMCMs and PLLs may be driven by the 200MHz input clock. For a full description of these rules and of the capabilities of the Kintex-7 clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” ([[http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf|ug472]]) available from Xilinx.+The Sword board includes several oscillators and crystals, of which one is connected to the FPGA. One differential LVDS 200MHz oscillator is connected to MRCC GPIO pins AD12/AD11 in bank 33. The clock can drive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. Some rules restrict which MMCMs and PLLs may be driven by the 200MHz input clock. For a full description of these rules and of the capabilities of the Kintex-7 clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” ([[https://docs.xilinx.com/v/u/en-US/ug472_7Series_Clocking|ug472]]) available from Xilinx.
  
 Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy-to-use wrapper component around these clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Vivado and IP Integrator tools. Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy-to-use wrapper component around these clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Vivado and IP Integrator tools.
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 //Table 22.1.1. Shield Voltage Specifications// //Table 22.1.1. Shield Voltage Specifications//
  
-For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://www.xilinx.com/support/documentation/data_sheets/ds182_kintex_7_data_sheet.pdf|Kintex-7 datasheet]] from Xilinx.+For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://docs.xilinx.com/v/u/en-US/ds182_Kintex_7_Data_Sheet|Kintex-7 datasheet]] from Xilinx.
  
 The pins on the shield connector typically used for I2C signals are labeled as SCL and SDA. When using these signals to implement an I2C bus it is necessary to attach a pull-up resistor to them. On the Sword, this can be done by placing two shorting blocks horizontally across the J4 header. The pins on the shield connector typically used for I2C signals are labeled as SCL and SDA. When using these signals to implement an I2C bus it is necessary to attach a pull-up resistor to them. On the Sword, this can be done by placing two shorting blocks horizontally across the J4 header.