This is an old revision of the document!

Nexys Video XADC Demo

Under Construction

Description

This project is a Vivado demo using the Nexys Video's analog-to-digital converter ciruitry, and the OLED display, written in Verilog. When programmed onto the board, voltage levels between 0 and 1 Volt are read off of the JXADC header. The OLED display shows the voltage difference between the appropriate channel's pins in volts.

The selected channels and pins are as follows:

XADC Channel JXADC Pins
AD1 JXADC1(P) / JXADC7(N)
AD0 JXADC2(P) / JXADC8(N)
AD8 JXADC3(P) / JXADC9(N)
AD9 JXADC4(P) / JXADC10(N)

Inventory

  • Nexys Video
  • A MicroUSB Cable
  • Vivado installation compatible with the latest release of this demo (2020.1)
  • Nexys Video 12 Volt Power Supply
  • Wires and a circuit to measure

Download and Usage Instructions

First and foremost, releases - consisting of a set of files for download - are only compatible with a specific version of the Xilinx tools, as specified in the name of the release (referred to as a release tag). In addition, releases are only compatible with the specified variant of the board. For example, a release tagged “20/DMA/2020.1” for the Zybo Z7 is only to be used with the -20 variant of the board and Vivado 2020.1.

The latest release version for this demo is highlighted in green.

Note: Releases for FPGA demos from before 2020.1 used a different git structure, and used a different release tag naming scheme.

Board Variant Release Tag Release Downloads Setup Instructions
Nexys Video XADC/2020.1-1 Release ZIP Downloads See Using the Latest Release, below
Nexys Video v2018.2-1 Release ZIP downloads v2018.2-1 Github README
Nexys Video v2016.4-1 Release ZIP downloads Using Digilent Github Demo Projects (Legacy)

Note for Advanced Users: All demos for the Nexys Video are provided through the Nexys Video repository on Github. Further documentation on the structure of this repository can be found on this wiki's Digilent FPGA Demo Git Repositories (Redirect) page.

Instructions on the use of the latest release can be found in this dropdown:

Using the Latest Release
This page has been moved, the new location is Using a Digilent FPGA Github Demo's Releases (2020.1).
Set up the Nexys Video
Plug the 12V Power Supply into the Nexys Video.

Plug the MicroUSB into the PROG port.

The circuit and wires can be attached after the demo is already running.

This page has been moved, the new location is Using a Digilent FPGA Github Demo's Releases (2020.1).

At this point, the demo is now running on your board. Refer to the Description and Functionality sections of this document for more information on what it does.

Functionality

1. Applying a Voltage to the XADC Port

For this demo, the AD1, AD0, AD8, and AD9 differential inputs on the JXADC header are used. We constructed a resistor ladder to connect each of the four channels' p pins to a Voltage level between zero and one, using one of the Pmod Ports to supply 3.3 Volts to the circuit. Each of the channels' n pins were grounded.

2. OLED Display

The OLED display shows the Voltage differential across each of the xadc pin pairs located on JXADC.

Important

Before turning off or reprogramming your board, shut down the OLED display by pressing the CPU_RESET button.

Additional Resources

All materials related to the use of the Nexys Video can be found on its Resource Center.

For a walkthrough of the process of creating a simple HDL project in Vivado, see Getting Started with Vivado for Hardware-Only Designs (Redirect). Information on important parts of the GUI, and indirect discussion of the steps required to modify, rebuild, and run this demo in hardware can also be found here.

For technical support, please visit the FPGA section of the Digilent Forum. 

{{tag>project nexys-video}}