Nexys Video DMA Audio Demo

This project demonstrates how to use the Nexys Video's Audio Codec and RAM to record samples of audio and play them back. Data is transferred to and from the DDR memory through DMA transfers. A custom I2S IP is used to control the timing of the transfers and to interface with the codec. Vivado is used to build the demo's hardware platform, and Vitis is used to program the bitstream onto the board and to build and deploy a C application.

• Nexys Video
• MicroUSB cables for programming and serial communication
• External power supply
• Audio input and output, such as audio cables with a phone or computer, microphone, and/or speakers.
• Vivado and Vitis installations compatible with the latest release of this demo (2020.1)
  • See Installing Vivado, Vitis, and Digilent Board Files for installation instructions.
• Serial Terminal application to receive messages printed by the demo
  • See Installing and Using a Terminal Emulator (Redirect) for more information.

First and foremost, releases - consisting of a set of files for download - are only compatible with a specific version of the Xilinx tools, as specified in the name of the release (referred to as a release tag). In addition, releases are only compatible with the specified variant of the board. For example, a release tagged “20/DMA/2020.1” for the Zybo Z7 is only to be used with the -20 variant of the board and Xilinx tools (Vivado and Vitis) version 2020.1.

The latest release version for this demo is highlighted in green.

Note: Releases for FPGA demos from before 2020.1 used a different git structure, and used a different release tag naming scheme.

Note for Advanced Users: All demos for the Nexys Video are provided through the Nexys-Video repository on Github. Further documentation on the structure of this repository can be found on this wiki's Digilent FPGA Demo Git Repositories (Redirect) page.

Instructions on the use of the latest release can be found in this dropdown:

Using the Latest Release

This page has been moved, the new location is Using a Digilent FPGA Github Demo's Releases (2020.1).

Set up the (Board)

Plug the Nexys Video into the computer via the MicroUSB programming cables (one for communication, one for programming). Plug the power supply into the board and power the board on by flipping the power switch.

Connect your audio equipment to the corresponding ports - MIC for microphones, HPH OUT for headphones or speakers, LINE IN/OUT for audio cables running to other devices.

Connect a serial terminal to the port associated with the Nexys Video. The demo uses a baud rate of 115200.

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This page has been moved, the new location is Using a Digilent FPGA Github Demo's Releases (2020.1).

At this point, the demo is now running on your board. Refer to the Description section of this document for more information on what it does.

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Additional steps beyond here present how you can use the other archive provided in the release, containing the hardware project, to rebuild the Vivado project, and use a newly exported XSA file to update the platform in Vitis.

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This page has been moved, the new location is Using a Digilent FPGA Github Demo's Releases (2020.1).

Audio playback and recording are controlled by push buttons as below.

Press the record button associated with the input you want to record from. Once the recording is activated, the message “Start Recording…” will be sent over UART and the demo will record 5 seconds of audio. If any buttons are pressed during the recording, the message “Still Recording…” will be sent over UART.

Press the play button associated with the output jack you want to use. Once the playback is activated, the message “Start Playback…” will be sent over UART and the demo will play 5 seconds of audio. If any buttons are pressed during the playback, the message “Still Playing…” will be sent over UART.

Note: Recording audio prior to playback is recommended, as the memory buffer used is not necessarily zeroed out when the application is launched, and loud static may be played.

All materials related to the use of the Nexys Video can be found on its Resource Center.

For a walkthrough of the process of creating a simple baremetal software project in Vivado and Vitis, see Getting Started with Vivado IP Integrator and Vitis (Redirect). Information on important parts of the GUIs, and indirect discussion of the steps required to modify, rebuild, and run this demo in hardware can also be found here.

For technical support, please visit the FPGA section of the Digilent Forum.

{{tag>project zybo-z7}}