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| programmable-logic:nexys-a7:reference-manual [2022/03/17 12:58] – unit spacing Arthur Brown | programmable-logic:nexys-a7:reference-manual [2022/10/04 04:38] (current) – external edit 127.0.0.1 | ||
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| The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience, | The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience, | ||
| - | For more details on the Xilinx memory interface solutions, refer to the 7 Series FPGAs Memory Interface Solutions User Guide (ug586)¹. | + | For more details on the Xilinx memory interface solutions, refer to the 7 Series FPGAs Memory Interface Solutions User Guide (ug586) |
| + | ¹. | ||
| ==== 3.2 Quad-SPI Flash ==== | ==== 3.2 Quad-SPI Flash ==== | ||
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| To find out the exact memory part loaded, check the PCB revision and any stickers placed on the PCB with the flash part number printed on it. The table below lists the possible load options. | To find out the exact memory part loaded, check the PCB revision and any stickers placed on the PCB with the flash part number printed on it. The table below lists the possible load options. | ||
| - | ^ Manufacturer | + | ^ Manufacturer |
| - | | Spansion/ | + | | Spansion/ |
| - | | Spansion/ | + | | Spansion/ |
| //Table 3.2.1 Flash memory part loaded// | //Table 3.2.1 Flash memory part loaded// | ||
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| //Figure 3.2.1 Nexys A7 SPI Flash Pin-out// | //Figure 3.2.1 Nexys A7 SPI Flash Pin-out// | ||
| - | ¹[[http://www.xilinx.com/ | + | ¹[[https://docs.xilinx.com/ |
| ²[[https:// | ²[[https:// | ||
| [[https:// | [[https:// | ||
| - | ³[[http://www.xilinx.com/ | + | ³[[https://docs.xilinx.com/ |