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| programmable-logic:nexys-a7:reference-manual [2021/12/29 06:25] – [3.2 Quad-SPI Flash] Added Flash memory part identification and differences. Elod Gyorgy | programmable-logic:nexys-a7:reference-manual [2022/10/04 04:38] (current) – external edit 127.0.0.1 | ||
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| * Download this reference manual: {{ : | * Download this reference manual: {{ : | ||
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| The only difference between the Nexys A7 and Nexys 4 DDR is the addition of the Nexys A7-50T variant of the Nexys A7, which has a smaller gate array. The Nexys A7-100T variant is functionally identical to the Nexys 4 DDR. | The only difference between the Nexys A7 and Nexys 4 DDR is the addition of the Nexys A7-50T variant of the Nexys A7, which has a smaller gate array. The Nexys A7-100T variant is functionally identical to the Nexys 4 DDR. | ||
| - | Users of the Nexys A7 may find resources produced for the Nexys 4 DDR helpful, which can be found at the Nexys 4 DDR's [[programmable-logic: | + | Users of the Nexys A7 may find resources produced for the Nexys 4 DDR helpful, which can be found at the Nexys 4 DDR's [[programmable-logic: |
| ==== Migrating from Nexys 4 ==== | ==== Migrating from Nexys 4 ==== | ||
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| The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, | The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, | ||
| - | Programming the Nexys A7 with an uncompressed bitstream using the on-board USB-JTAG circuitry usually takes around five seconds. JTAG programming can be done using the hardware server in Vivado or the iMPACT tool included with ISE and the Lab Tools version of Vivado. | + | Programming the Nexys A7 with an uncompressed bitstream using the on-board USB-JTAG circuitry usually takes around five seconds. JTAG programming can be done using the hardware server in Vivado or the iMPACT tool included with ISE and the Lab Tools version of Vivado. |
| ==== 2.2 Quad-SPI Configuration ==== | ==== 2.2 Quad-SPI Configuration ==== | ||
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| The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience, | The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience, | ||
| - | For more details on the Xilinx memory interface solutions, refer to the 7 Series FPGAs Memory Interface Solutions User Guide (ug586)¹. | + | For more details on the Xilinx memory interface solutions, refer to the 7 Series FPGAs Memory Interface Solutions User Guide (ug586) |
| + | ¹. | ||
| ==== 3.2 Quad-SPI Flash ==== | ==== 3.2 Quad-SPI Flash ==== | ||
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| The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. All signals in the SPI bus except SCK are general-purpose user I/O pins after FPGA configuration. SCK is an exception because it remains a dedicated pin even after configuration. Access to this pin is provided through a special FPGA primitive called STARTUPE2. | The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. All signals in the SPI bus except SCK are general-purpose user I/O pins after FPGA configuration. SCK is an exception because it remains a dedicated pin even after configuration. Access to this pin is provided through a special FPGA primitive called STARTUPE2. | ||
| - | To find out the exact memory part loaded, check the PCB revision | + | To find out the exact memory part loaded, check the PCB revision and any stickers placed |
| - | ^ Manufacturer | + | ^ Manufacturer |
| - | | Spansion/ | + | | Spansion/ |
| - | | Spansion/ | + | | Spansion/ |
| //Table 3.2.1 Flash memory part loaded// | //Table 3.2.1 Flash memory part loaded// | ||
| - | The two part numbers are highly compatible and the " | + | The two part numbers are highly compatible and the " |
| A non-exhaustive list of the differences between the S25FL127S and the S25FL128S: | A non-exhaustive list of the differences between the S25FL127S and the S25FL128S: | ||
| * Read SFDP command (5Ah) is supported now. The Linux kernel driver is known to probe this command and use the SFDP feature to dynamically initialize the flash device instead of relying on a static configuration if the command is available. | * Read SFDP command (5Ah) is supported now. The Linux kernel driver is known to probe this command and use the SFDP feature to dynamically initialize the flash device instead of relying on a static configuration if the command is available. | ||
| * DDR Fast Read (0Dh, 0Eh), DDR Dual I/O Read (BDh, BEh), and Read DDR Quad I/O (EDh, EEh) not supported | * DDR Fast Read (0Dh, 0Eh), DDR Dual I/O Read (BDh, BEh), and Read DDR Quad I/O (EDh, EEh) not supported | ||
| * Memory organization: | * Memory organization: | ||
| - | * Maximum clock frequency: 108 MHz vs. 133MHz. Practically however, the system board limit is usually lower. The 50 MHz read/write maximum frequency of the Nexys A7 applies. | + | * Maximum clock frequency: 108 MHz vs. 133 MHz. Practically however, the system board limit is usually lower. The 50 MHz read/write maximum frequency of the Nexys A7 applies. |
| **NOTE: Refer to the manufacturer’s data sheets² | **NOTE: Refer to the manufacturer’s data sheets² | ||
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| //Figure 3.2.1 Nexys A7 SPI Flash Pin-out// | //Figure 3.2.1 Nexys A7 SPI Flash Pin-out// | ||
| - | ¹[[http://www.xilinx.com/ | + | ¹[[https://docs.xilinx.com/ |
| ²[[https:// | ²[[https:// | ||
| [[https:// | [[https:// | ||
| - | ³[[http://www.xilinx.com/ | + | ³[[https://docs.xilinx.com/ |
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| Two on-board LEDs (LD23 = LED2, LD24 = LED1) connected to the PHY provide link status and data activity feedback. See the PHY datasheet for details. | Two on-board LEDs (LD23 = LED2, LD24 = LED1) connected to the PHY provide link status and data activity feedback. See the PHY datasheet for details. | ||
| - | EDK-based designs can access the PHY using either the axi_ethernetlite (AXI EthernetLite) IP core or the axi_ethernet (Tri Mode Ethernet MAC) IP core. A mii_to_rmii core (Ethernet PHY MII to Reduced MII) needs to be inserted to convert the MAC interface from MII to RMII. Also, a 50 MHz clock needs to be generated for the mii_to_rmii core and the CLKIN pin of the external PHY. To account for skew introduced by the mii_to_rmii core, generate each clock individually, | + | EDK-based designs can access the PHY using either the axi_ethernetlite (AXI EthernetLite) IP core or the axi_ethernet (Tri Mode Ethernet MAC) IP core. A mii_to_rmii core (Ethernet PHY MII to Reduced MII) needs to be inserted to convert the MAC interface from MII to RMII. Also, a 50 MHz clock needs to be generated for the mii_to_rmii core and the CLKIN pin of the external PHY. To account for skew introduced by the mii_to_rmii core, generate each clock individually, |
| ISE designs can use the IP Core Generator wizard to create an Ethernet MAC controller IP core. | ISE designs can use the IP Core Generator wizard to create an Ethernet MAC controller IP core. | ||
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| | JA10: G18 | JB10: H16 | JC10: E6 | JD10: F3 | JXADC10: A18 (AD11N) | | JA10: G18 | JB10: H16 | JC10: E6 | JD10: F3 | JXADC10: A18 (AD11N) | ||
| - | Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod expansion connectors to add ready-made functions like A/D’s, D/A’s, motor drivers, sensors, as well as other functions. See www.digilentinc.com | + | Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod expansion connectors to add ready-made functions like A/D’s, D/A’s, motor drivers, sensors, as well as other functions. See the [[/ |
| ==== 10.1 Dual Analog/ | ==== 10.1 Dual Analog/ | ||