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programmable-logic:nexys-a7:reference-manual [2021/11/19 12:03] – [1.1 Protection] Change occurrence of 'Figure 2' to 'Figure 1.1' Andrew Holzerprogrammable-logic:nexys-a7:reference-manual [2022/10/04 04:38] (current) – external edit 127.0.0.1
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 +=====%hide download=====
  
   * Download this reference manual: {{ :reference:programmable-logic:nexys-a7:nexys-a7_rm.pdf | PDF}}   * Download this reference manual: {{ :reference:programmable-logic:nexys-a7:nexys-a7_rm.pdf | PDF}}
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 The only difference between the Nexys A7 and Nexys 4 DDR is the addition of the Nexys A7-50T variant of the Nexys A7, which has a smaller gate array. The Nexys A7-100T variant is functionally identical to the Nexys 4 DDR. The only difference between the Nexys A7 and Nexys 4 DDR is the addition of the Nexys A7-50T variant of the Nexys A7, which has a smaller gate array. The Nexys A7-100T variant is functionally identical to the Nexys 4 DDR.
  
-Users of the Nexys A7 may find resources produced for the Nexys 4 DDR helpful, which can be found at the Nexys 4 DDR's [[programmable-logic:nexys-a7:start|Resource Center]].+Users of the Nexys A7 may find resources produced for the Nexys 4 DDR helpful, which can be found at the Nexys 4 DDR's [[programmable-logic:nexys-4-ddr:start|Resource Center]].
  
 ==== Migrating from Nexys 4 ==== ==== Migrating from Nexys 4 ====
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 The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using the onboard Digilent USB-JTAG circuitry (port J6) or an external JTAG programmer, such as the Digilent JTAG-HS2, attached to port J10. You can perform JTAG programming any time after the Nexys A7 has been powered on, regardless of what the mode jumper (JP1) is set to. If the FPGA is already configured, then the existing configuration is overwritten with the bitstream being transmitted over JTAG. Setting the mode jumper to the JTAG setting (seen in Figure 2.1) is useful to prevent the FPGA from being configured from any other bitstream source until a JTAG programming occurs. The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using the onboard Digilent USB-JTAG circuitry (port J6) or an external JTAG programmer, such as the Digilent JTAG-HS2, attached to port J10. You can perform JTAG programming any time after the Nexys A7 has been powered on, regardless of what the mode jumper (JP1) is set to. If the FPGA is already configured, then the existing configuration is overwritten with the bitstream being transmitted over JTAG. Setting the mode jumper to the JTAG setting (seen in Figure 2.1) is useful to prevent the FPGA from being configured from any other bitstream source until a JTAG programming occurs.
  
-Programming the Nexys A7 with an uncompressed bitstream using the on-board USB-JTAG circuitry usually takes around five seconds. JTAG programming can be done using the hardware server in Vivado or the iMPACT tool included with ISE and the Lab Tools version of Vivado. The demonstration project available at www.digilentinc.com gives an in-depth tutorial on how to program your board. +Programming the Nexys A7 with an uncompressed bitstream using the on-board USB-JTAG circuitry usually takes around five seconds. JTAG programming can be done using the hardware server in Vivado or the iMPACT tool included with ISE and the Lab Tools version of Vivado. Demonstration projects available through the [[start|Nexys A7 Resource Center]] gives an in-depth tutorial on how to program your board.
  
 ==== 2.2 Quad-SPI Configuration ==== ==== 2.2 Quad-SPI Configuration ====
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 The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience, an importable UCF file is provided on the Digilent website to speed up the process. The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience, an importable UCF file is provided on the Digilent website to speed up the process.
  
-For more details on the Xilinx memory interface solutions, refer to the 7 Series FPGAs Memory Interface Solutions User Guide (ug586)¹.+For more details on the Xilinx memory interface solutions, refer to the 7 Series FPGAs Memory Interface Solutions User Guide (ug586) 
 +¹.
  
 ==== 3.2 Quad-SPI Flash ==== ==== 3.2 Quad-SPI Flash ====
  
-FPGA configuration files can be written to the Quad-SPI Flash (Spansion part number S25FL128S), and mode settings are available to cause the FPGA to automatically read a configuration from this device at power on. An Artix-7 100T configuration file requires just less than four MiB (mebibyte) of memory, leaving about 77% of the flash device available for user data. Or, if the FPGA is getting configured from another source, the whole memory can be used for custom data.+FPGA configuration files can be written to the Quad-SPI Flash, and mode settings are available to cause the FPGA to automatically read a configuration from this device at power on. An Artix-7 100T configuration file requires just less than four MiB (mebibyte) of memory, leaving about 77% of the flash device available for user data. Or, if the FPGA is getting configured from another source, the whole memory can be used for custom data.
  
 The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. All signals in the SPI bus except SCK are general-purpose user I/O pins after FPGA configuration. SCK is an exception because it remains a dedicated pin even after configuration. Access to this pin is provided through a special FPGA primitive called STARTUPE2. The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. All signals in the SPI bus except SCK are general-purpose user I/O pins after FPGA configuration. SCK is an exception because it remains a dedicated pin even after configuration. Access to this pin is provided through a special FPGA primitive called STARTUPE2.
 +
 +To find out the exact memory part loaded, check the PCB revision and any stickers placed on the PCB with the flash part number printed on it. The table below lists the possible load options.
 +
 +^ Manufacturer       ^ P/N                       | PCB Revision                       | Package Marking  |
 +| Spansion/Infineon  | S25FL128SAG[M%%|%%N]FI00  | ≤ D w/o sticker OR ≥ D w/ sticker  | FL128SAIF00      |
 +| Spansion/Infineon  | S25FL127SABMFx00          | ≥ D w/ sticker                     | FL127SxF00       |
 +//Table 3.2.1 Flash memory part loaded//
 +
 +The two part numbers are highly compatible and the "s25fl128s-3.3v-qspi-x4-single" part configuration can be used in Vivado Hardware Manager for both. However, the S25FL127S is not functionally equivalent to the S25FL128S and might require changes to customer applications (embedded software) depending on the board support package in use (OS, drivers, and libraries). It might be possible to implement any changes that might be needed in such a way to keep compatibility with all load options.
 +A non-exhaustive list of the differences between the S25FL127S and the S25FL128S:
 +  * Read SFDP command (5Ah) is supported now. The Linux kernel driver is known to probe this command and use the SFDP feature to dynamically initialize the flash device instead of relying on a static configuration if the command is available.
 +  * DDR Fast Read (0Dh, 0Eh), DDR Dual I/O Read (BDh, BEh), and Read DDR Quad I/O (EDh, EEh) not supported
 +  * Memory organization: 255 64-KB and 16 4-KB bottom hybrid erase sectors vs. 254 64-KB and 32 4-KB bottom hybrid erase sectors
 +  * Maximum clock frequency: 108 MHz vs. 133 MHz. Practically however, the system board limit is usually lower. The 50 MHz read/write maximum frequency of the Nexys A7 applies.
  
 **NOTE: Refer to the manufacturer’s data sheets²  and Xilinx user guides³  for more information.** **NOTE: Refer to the manufacturer’s data sheets²  and Xilinx user guides³  for more information.**
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 //Figure 3.2.1 Nexys A7 SPI Flash Pin-out// //Figure 3.2.1 Nexys A7 SPI Flash Pin-out//
  
-¹[[http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_1/ug586_7Series_MIS.pdf|Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions from Xilinx]]+¹[[https://docs.xilinx.com/v/u/2.1-English/ug586_7Series_MIS|Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions from Xilinx]]
  
-²[[https://www.spansion.com/Support/Datasheets/S25FL032P_00.pdf| Spansion S25FL032P_00 Datasheet]]+²[[https://www.infineon.com/dgdl/Infineon-S25FL128S_S25FL256S_128_Mb_(16_MB)_256_Mb_(32_MB)_3.0V_SPI_Flash_Memory-DataSheet-v18_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecfb6a64a17&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-files|Spansion S25FL128S Datasheet]] 
 +[[https://www.infineon.com/dgdl/Infineon-S25FL127S_128-Mb_(16_MB)_3.0_V_SPI_Flash_Memory-DataSheet-v11_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecfa58c49f7&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-datasheet|Spansion S25FL127S Datasheet]]
  
-³[[http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf|7-Series FPGAs Configuration User Guide from Xilinx]]+³[[https://docs.xilinx.com/v/u/FOs3lXmlcWxBhTIFxVKyGA|7-Series FPGAs Configuration User Guide from Xilinx]]
  
  
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 Two on-board LEDs (LD23 = LED2, LD24 = LED1) connected to the PHY provide link status and data activity feedback. See the PHY datasheet for details. Two on-board LEDs (LD23 = LED2, LD24 = LED1) connected to the PHY provide link status and data activity feedback. See the PHY datasheet for details.
  
-EDK-based designs can access the PHY using either the axi_ethernetlite (AXI EthernetLite) IP core or the axi_ethernet (Tri Mode Ethernet MAC) IP core. A mii_to_rmii core (Ethernet PHY MII to Reduced MII) needs to be inserted to convert the MAC interface from MII to RMII. Also, a 50 MHz clock needs to be generated for the mii_to_rmii core and the CLKIN pin of the external PHY. To account for skew introduced by the mii_to_rmii core, generate each clock individually, with the external PHY clock having a 45 degree phase shift relative to the mii_to_rmii Ref_Clk. An EDK demonstration project that properly uses the Ethernet PHY can be found on the Nexys A7 product page at www.digilentinc.com.+EDK-based designs can access the PHY using either the axi_ethernetlite (AXI EthernetLite) IP core or the axi_ethernet (Tri Mode Ethernet MAC) IP core. A mii_to_rmii core (Ethernet PHY MII to Reduced MII) needs to be inserted to convert the MAC interface from MII to RMII. Also, a 50 MHz clock needs to be generated for the mii_to_rmii core and the CLKIN pin of the external PHY. To account for skew introduced by the mii_to_rmii core, generate each clock individually, with the external PHY clock having a 45 degree phase shift relative to the mii_to_rmii Ref_Clk.
  
 ISE designs can use the IP Core Generator wizard to create an Ethernet MAC controller IP core.  ISE designs can use the IP Core Generator wizard to create an Ethernet MAC controller IP core. 
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 | JA10: G18                                       | JB10: H16    | JC10: E6     | JD10: F3     | JXADC10: A18 (AD11N)  | | JA10: G18                                       | JB10: H16    | JC10: E6     | JD10: F3     | JXADC10: A18 (AD11N)  |
  
-Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod expansion connectors to add ready-made functions like A/D’s, D/A’s, motor drivers, sensors, as well as other functions. See www.digilentinc.com for more information.+Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod expansion connectors to add ready-made functions like A/D’s, D/A’s, motor drivers, sensors, as well as other functions. See the [[/pmod/start|Pmod]] page of Digilent Reference for more information.
  
 ==== 10.1 Dual Analog/Digital Pmod ==== ==== 10.1 Dual Analog/Digital Pmod ====