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programmable-logic:nexys-a7:demos:xadc [2021/05/14 23:07] – ↷ Links adapted because of a move operation Arthur Brownprogrammable-logic:nexys-a7:demos:xadc [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 ====== Nexys A7 XADC Demo ====== ====== Nexys A7 XADC Demo ======
- 
-<WRAP todo important> 
-== Under Construction == 
-</WRAP> 
  
 {{:reference:programmable-logic:nexys-a7:demos:nexys_xadc.jpg?600|}} {{:reference:programmable-logic:nexys-a7:demos:nexys_xadc.jpg?600|}}
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 ===== Description ===== ===== Description =====
-This project is a Vivado demo using the Nexys A7-100T's analog-to-digital converter ciruitry, switches, LEDs, and seven-segment display, written in Verilog. When programmed onto the board, voltage levels between 0 and 1 Volt are read off of the JXADC header. The 16 User LEDs increment from right to left as the voltage difference between the selected channel's pins gets larger. The seven-segment display shows the voltage difference between the selected channel's pins in volts. SW0 and SW1 select which XADC channel is displayed. +This project is a Vivado demo using the Nexys A7-100T's analog-to-digital converter circuitry, switches, LEDs, and seven-segment display, written in Verilog. When programmed onto the board, voltage levels between 0 and 1 Volt are read off of the JXADC header. The 16 User LEDs increment from right to left as the voltage difference between the selected channel's pins gets larger. The seven-segment display shows the voltage difference between the selected channel's pins in volts. SW0 and SW1 select which XADC channel is displayed.
- +
-See the Nexys A7's [[https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/reference-manual|Reference Manual]] for more information about how the Artix 7 FPGA's XADC is connected to header JXADC.+
  
-Additional information on how this demo can be used can be found in appropriate READMEs, linked below.+See the Nexys A7's [[programmable-logic/nexys-a7/reference-manual|Reference Manual]] for more information about how the Artix 7 FPGA's XADC is connected to header JXADC.
  
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   * Nexys A7 with a MicroUSB Programming Cable   * Nexys A7 with a MicroUSB Programming Cable
   * Vivado installation compatible with the latest release of this demo (2020.1)   * Vivado installation compatible with the latest release of this demo (2020.1)
-    * //See [[programmable-logic:guides:installation|Installing Vivado, Vitis, and Digilent Board Files]] for installation instructions.//+    * //See [[programmable-logic:guides:installing-vivado-and-vitis|Installing Vivado, Vitis, and Digilent Board Files]] for installation instructions.//
   * Wires, Breadboard and a Circuit to Test   * Wires, Breadboard and a Circuit to Test
  
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 ==== 1. LEDs and Switches ==== ==== 1. LEDs and Switches ====
  
-The demo reads analog data in from each enabled XADC channel (set using sw0 and sw1).  The 7-Segment display shows the current voltage across the selected xadc pins. The LEDs turn on from right to left as the input voltage increases.+The demo reads analog data from each enabled XADC channel (set using sw0 and sw1).  The 7-Segment display shows the current voltage across the selected xadc pins. The LEDs turn on from right to left as the input voltage increases. The switch selections for each channel can be seen in the table below: 
 + 
 +|<60% 20% 20% 20%>| 
 +^ Channel ^ Pin ^ SW0 / SW1 Positions | 
 +| AD2P/N | XA3 | Down / Down ^ 
 +| AD3P/N | XA1 | Up / Down ^ 
 +| AD10P/N | XA2 | Down / Up ^ 
 +| AD11P/N | XA4 | Up / Up ^
  
 ==== 2. Setting up the Circuit ==== ==== 2. Setting up the Circuit ====
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-<code>{{tag>project nexys-a7}}</code>