Nexys A7 DMA Audio Demo

This project demonstrates how to stream data in and out of the Nexys A7's RAM. Vivado is used to build the demo's hardware platform, and Vitis is used to program the bitstream onto the board and to build and deploy a C application.

Additional information on how this demo can be used can be found in appropriate READMEs, linked below.

• Nexys A7 with a MicroUSB Programming Cable
• Vivado and Vitis installations compatible with the latest release of this demo (2020.1)
  • See Installing Vivado, Vitis, and Digilent Board Files for installation instructions.
• Serial Terminal application to receive messages printed by the demo
  • See Installing and Using a Terminal Emulator (Redirect) for more information.
• Headphones or Speakers with 3.5mm Audio Jack

The following releases of this demo can be used with instructions found in the corresponding READMEs in order to run the demo.

Releases are only compatible with the version of the Xilinx tools specified in the release version number. In addition, releases are only compatible with the specified variant of the board. For example, the v2020.1-1 release for Nexys A7-100T can only be used with Vivado and Vitis 2020.1 and Nexys A7-100T variant of the board.

The latest release version for this demo is highlighted in green.

Note: Releases for FPGA demos from before 2020.1 used a different git structure, and used a different release tag naming scheme.

Note for Advanced Users: All demos for the Nexys A7 are provided through the Nexys-A7 repository on Github. Further documentation on the structure of this repository can be found on this wiki's Digilent FPGA Demo Git Repositories (Redirect) page.

Instructions on the use of the latest release can be found in this dropdown:

Using the Latest Release

This page has been moved, the new location is Using a Digilent FPGA Github Demo's Releases (2020.1).

Set up the Nexys A7

Plug the microUSB programming cable into the Nexys A7's PROG/UART port and the headphones or speakers into the MONO AUDIO OUT port.

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This page has been moved, the new location is Using a Digilent FPGA Github Demo's Releases (2020.1).

At this point, the demo is now running on your board. Refer to the Description section of this document for more information on what it does.

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Additional steps beyond here present how you can use the other archive provided in the release, containing the hardware project, to rebuild the Vivado project, and use a newly exported XSA file to update the platform in Vitis.

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This page has been moved, the new location is Using a Digilent FPGA Github Demo's Releases (2020.1).

All materials related to the use of the Nexys A7 can be found on its Resource Center.

For a walkthrough of the process of creating a simple baremetal software project in Vivado and Vitis, see Getting Started with Vivado IP Integrator and Vitis (Redirect). Information on important parts of the GUIs, and indirect discussion of the steps required to modify, rebuild, and run this demo in hardware can also be found here.

For technical support, please visit the FPGA section of the Digilent Forum.

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