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programmable-logic:guides:vivado-add-microblaze [2021/07/30 22:03] – Arthur Brownprogrammable-logic:guides:vivado-add-microblaze [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 **Note:** //This section is intended for use with boards without a Zynq chip. For Zynq boards, the Zynq7 Processing System should be used instead.// **Note:** //This section is intended for use with boards without a Zynq chip. For Zynq boards, the Zynq7 Processing System should be used instead.//
 +
 +**Note:** //If you aren't sure whether your board has DDR memory, check the //Memory// column of the specification table on this site's [[programmable-logic:start]] page.//
  
 --> Follow the steps in this dropdown for boards without DDR memory # --> Follow the steps in this dropdown for boards without DDR memory #
 <WRAP group> <WRAP group>
 <WRAP group> <WRAP column half> <WRAP group> <WRAP column half>
-First, an external clock should be added to the block design, so that it can be used to generate any other clocks required by the design. Open the **Board** tab, and find the system clock. Right click on it and select **Connect Board Component**.+First, an external clock should be added to the block design, so that it can be used to generate any other clocks required by the design. Open the **Board** tab, and find the system clock. Right-click on it and select **Connect Board Component**.
 </WRAP> <WRAP column half> </WRAP> <WRAP column half>
 {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-1.png?600 |}} {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-1.png?600 |}}
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 Click **OK** to confirm your changes to the Clocking Wizard's settings. Click **OK** to confirm your changes to the Clocking Wizard's settings.
  
-**Note:** //This section can always be returned to later, as the addition of an additional clock can be performed any time before the hardware is built.//+If you aren't sure that you have all of the clocks you need, don't worry, you can always come back and add them by reconfiguring this IP. This task can be performed whenever in the design process it becomes necessary.
  
 </WRAP> <WRAP column half> </WRAP> <WRAP column half>