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programmable-logic:guides:vivado-add-microblaze [2021/05/14 23:04] – ↷ Page moved from reference:programmable-logic:guides:vivado-add-microblaze to programmable-logic:guides:vivado-add-microblaze Arthur Brownprogrammable-logic:guides:vivado-add-microblaze [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 **Note:** //This section is intended for use with boards without a Zynq chip. For Zynq boards, the Zynq7 Processing System should be used instead.// **Note:** //This section is intended for use with boards without a Zynq chip. For Zynq boards, the Zynq7 Processing System should be used instead.//
  
 +**Note:** //If you aren't sure whether your board has DDR memory, check the //Memory// column of the specification table on this site's [[programmable-logic:start]] page.//
 +
 +--> Follow the steps in this dropdown for boards without DDR memory #
 +<WRAP group>
 <WRAP group> <WRAP column half> <WRAP group> <WRAP column half>
-First, an external clock should be added to the block design, so that it can be used to generate any other clocks required by the design. Open the **Board** tab, and find the system clock. Right click on it and select **Connect Board Component**.+First, an external clock should be added to the block design, so that it can be used to generate any other clocks required by the design. Open the **Board** tab, and find the system clock. Right-click on it and select **Connect Board Component**.
 </WRAP> <WRAP column half> </WRAP> <WRAP column half>
 {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-1.png?600 |}} {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-1.png?600 |}}
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 ---- ----
  
-Two flows are available, depending on whether your board has DDR memory. If the board has DDR, a DDR interface will appear in Vivado's Board tab. Choose the appropriate dropdown, below:+<WRAP group> <WRAP column half> 
 +Your design will require at least one clock from the clocking wizard. If your design requires more clocks, then they must be added through the Clocking Wizard.
  
---> Adding a DDR Interface #+Double click on the Clocking Wizard IP core to edit its settings. Navigate to the //Output Clocks// tab. Additional clocks are added to the Clocking Wizard by checking a box in the //Output Clock// column, and specifying a //Requested Output Frequency//. Additionally, if desired, the ports can be named according to their intended purpose.
  
-<WRAP round todo> +If your design requires additional clocks (such as for an ext_spi_clock pin), they should be added now.
-This section is undergoing significant rework, in order to better match Xilinx design guidelines, and should not be considered a comprehensive guide to connecting a MIG IP to a Microblaze processor. This rework is anticipated to be complete by August 21, 2020. +
-</WRAP>+
  
 +Click **OK** to confirm your changes to the Clocking Wizard's settings.
 +
 +If you aren't sure that you have all of the clocks you need, don't worry, you can always come back and add them by reconfiguring this IP. This task can be performed whenever in the design process it becomes necessary.
 +
 +</WRAP> <WRAP column half>
 +{{ :reference:programmable-logic:guides:microblaze-8.png?600 |}}
 +</WRAP> </WRAP>
 +
 +----
 <WRAP group> <WRAP column half> <WRAP group> <WRAP column half>
-Returning to the //Board// tab, your board may provide a DDR interface, which can be used with Xilinx's //Memory Interface Generator// (MIG) IP to provide the processor access to DDR memory. As when adding the system clock, right click on the DDR entry in the list and select **Connect Board Component**. In the pop up dialog, select the MIG's mig_ddr_interface, and click **OK** to continue.+Next, use the **Add IP** button ({{:learn:programmable-logic:tutorials:2020.1:add-zynq-processor:add-ip.png?nolink|}}) to add the //MicroBlaze// IP to the design. The block that is added represents the core of the Microblaze processor.
 </WRAP> <WRAP column half> </WRAP> <WRAP column half>
-{{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-6.png?600 |}}+{{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-12.png?600 |}}
 </WRAP> </WRAP> </WRAP> </WRAP>
 ---- ----
 <WRAP group> <WRAP column half> <WRAP group> <WRAP column half>
-Once the MIG has been added to the design, it will have been connected to one or more additional external ports, typically a reference clock (clk_ref_i) and system clock (sys_clk_i). As Digilent boards typically do not provide clocks dedicated for use with the MIG (to reduce the costs of additional oscillators, and to save FPGA pins for other interfaces), these external ports should be deleted. Select each these pins (but NOT the DDR port!), right click on one of them, and select **Delete** from the menu (or press the delete key on your keyboard).+Next, block automation will be run so that additional supporting infrastructure can be added to the design. Click **Run Block Automation** in the green //Designer Assistance// bar.
  
-The next few steps will discuss how to manually connect the MIG's clock pins to clocks generated by the Clocking Wizard.+**Note:** //The screenshot to the right is not representative for a design not using DDR, as these designs will not contain a MIG IP core.//
 </WRAP> <WRAP column half> </WRAP> <WRAP column half>
-{{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-7.png?600 |}}+{{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-13.png?600 |}}
 </WRAP> </WRAP> </WRAP> </WRAP>
 ---- ----
 <WRAP group> <WRAP column half> <WRAP group> <WRAP column half>
-Digilent's board files provide default settings for the MIG IP. Of note for this design are the clock frequencies that must be provided to the MIG's clock pins.+In the //Run Block Automation// dialog, several settings can be specified for how the Microblaze IP will be connected to the rest of the design: 
 +  * **Local Memory** specifies how much block RAM memory will be dedicated to the processor. DDR-less designs require more memory, and the amount of memory necessary depends heavily on the size of the software application being run. 32KB is enough for many small applications. 
 +  * **Cache Configuration** can help the speed of designs using DDR memory. It should be enabled when using DDR and disabled otherwise. 
 +  * **Debug Module** allows you to specify the capabilities of the debugger. The default //Debug Only// option is recommended. 
 +  * **Peripheral AXI Port** enables or disables the AXI master interface of the processor. It must be enabled to allow the processor to be connected to hardware peripherals. 
 +  * **Interrupt Controller** specifies whether the processor can be interrupted by its peripherals. Whether or not it needs to be enabled depends on your design requirements. If any IP that you intend to connect to the processor must have interrupts to function correctly, the box must be checked. 
 +  * **Clock Connection** specifies the processor's clock. Designs using DDR should use the MIG's ui_clk pin, while designs without DDR should use the Clocking Wizards clk_out1 pin.
  
-First, these clocks must be generated by the Clocking Wizard. Double click on the Clocking Wizard IP core to edit its settings. Navigate to the //Output Clocks// tab, and create clocks of the frequencies specified in the table below:+**Note:** //Settings not present in this list are out of the scope of this guide, and can safely be left as their default.//
  
-^ Board ^ MIG System Clock (sys_clk_i) Frequency ^ MIG Reference Clock (ref_clk_i) Frequency ^ +Confirm that the settings meet your design requirements. It should be noted that while it is possible to change these settings manually later (for example, by manually adding an AXI INTC IP and connecting it to the processor), the easiest way to do so will be to clear the Microblaze processor out of your block design and restart the process of adding the processor. This is to say, the settings chosen here are important. Getting them right the first time will save you time in the long run.
-| Arty A7 | 166.66667 MHz | 200 MHz | +
-| Arty S7 | 100 MHz | 200 MHz | +
-| Nexys A7 | 200 MHz | N/A | +
-| USB104 A7 | 200 MHz | N/A | +
-| Nexys Video | 200 MHz | N/A | +
-| Genesys 2 | 200 MHz | N/A | +
-| Sword | 200 MHz | N/A |+
  
-**Important:** //For the Arty S7, the MIG configuration provided by the board files is intended to have the MIG sys_clk pin driven by the //DDR Clock// board file interface, and have the ref_clk input driven by the MIG's ui_addn_clk_0 port. Refer to the [[reference:programmable-logic:arty-s7:start|Arty S7 Reference Manual]] for more information.// +Click **OK** to continue.
- +
-Output clocks are added to the Clocking Wizard by checking a box in the //Output Clock// column, and specifying a //Requested Output Frequency//. Additionally, if desired, the ports can be named according to their intended purpose. +
- +
-If your design requires additional clocks (such as for an ext_spi_clock pin), they should be added to the Clocking Wizard as well. +
- +
-**Note:** //This section can always be returned to later, as the addition of an additional clock can be performed any time before the hardware is built.// +
- +
-Click **OK** to confirm your changes to the Clocking Wizard's settings.+
 </WRAP> <WRAP column half> </WRAP> <WRAP column half>
-{{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-8.png?600 |}}+{{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-14.png?600 |}}
 </WRAP> </WRAP> </WRAP> </WRAP>
 +
 ---- ----
 <WRAP group> <WRAP column half> <WRAP group> <WRAP column half>
-Next, the Clocking Wizard's new output clocks should be connected to the MIG, based on the specified frequencies seen in the table in the last step. If needed, the frequency of a clock can be checked by selecting the Clocking Wizard's output pin, and looking at the //Block Pin Properties// pane to the left of the block diagram. +Next, in order for the software design to be able to print to a serial console on a host computer, a UART peripheral must be connected. Find the //USB UART// interface in the //Board// tab, right click on it, and select **Connect Board Component**.
- +
-Connect the clocks by clicking and dragging from one pin to the other, as seen in the image to the right.+
 </WRAP> <WRAP column half> </WRAP> <WRAP column half>
-{{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-10.png?600 |}}+{{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-18.png?600 |}}
 </WRAP> </WRAP> </WRAP> </WRAP>
 ---- ----
 <WRAP group> <WRAP column half> <WRAP group> <WRAP column half>
-Next, manually connect the MIG's sys_rst pin to the external reset port by clicking and dragging. Make sure that the polarity is correct. If necessary, a Utility Vector Logic IP can be added to the design to convert from an active high external reset to an active low MIG reset. +In the dialog that pops up, select a new AXI Uartlite IP's UART interface, and click **OK** to add the block to the diagram.
- +
-**Note:** //The image to the right shows an active low MIG reset (indicated by the "bubble" on the pin), being connected to an active low external reset.//+
 </WRAP> <WRAP column half> </WRAP> <WRAP column half>
-{{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-11.png?600 |}}+{{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-19.png?600 |}}
 </WRAP> </WRAP> </WRAP> </WRAP>
- +----
-<-- +
- +
---> Adding Additional Clocks (For Boards Without DDR) # +
 <WRAP group> <WRAP column half> <WRAP group> <WRAP column half>
-Your design will require at least one clock from the clocking wizard. If your design requires more clocks, then they must be added through the Clocking Wizard. +To connect all remaining AXI cores that have not yet been connected to the processor, click the **Run Connection Automation** button in the green //Designer Assistance// bar. Check the //All Automation// box in the list on the left side of the window to select all of the remaining AXI cores. The dropdown settings available for each core can safely be left as their default values. Click **OK** to automatically connect them to the processor.
- +
-Double click on the Clocking Wizard IP core to edit its settings. Navigate to the //Output Clocks// tab. Additional clocks are added to the Clocking Wizard by checking a box in the //Output Clock// column, and specifying a //Requested Output Frequency//. Additionally, if desired, the ports can be named according to their intended purpose. +
- +
-If your design requires additional clocks (such as for an ext_spi_clock pin), they should be added now. +
- +
-Click **OK** to confirm your changes to the Clocking Wizard's settings. +
- +
-**Note:** //This section can always be returned to later, as the addition of an additional clock can be performed any time before the hardware is built.// +
 </WRAP> <WRAP column half> </WRAP> <WRAP column half>
-{{ :reference:programmable-logic:guides:microblaze-8.png?600 |}}+{{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-20.png?600 |}}
 </WRAP> </WRAP> </WRAP> </WRAP>
 +</WRAP>
 <-- <--
  
 +--> Follow the steps in this dropdown for boards with DDR memory #
 +<WRAP group>
 +{{section>microblaze-adding-ddr#add_the_mig_ip&noheader}}
 +{{section>microblaze-adding-ddr#mig_clocking&noheader}}
 +{{section>microblaze-adding-ddr#mig_reset&noheader}}
 +{{section>microblaze-adding-ddr#other_mig_ports&noheader}}
 +{{section>microblaze-adding-ddr#additional_clocks&noheader}}
 +{{section>microblaze-adding-ddr#mig_success&noheader}}
 ---- ----
 <WRAP group> <WRAP column half> <WRAP group> <WRAP column half>
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 **Note:** //Settings not present in this list are out of the scope of this guide, and can safely be left as their default.// **Note:** //Settings not present in this list are out of the scope of this guide, and can safely be left as their default.//
  
-Confirm that the settings meet your design requirements. To rerun Block Automation, each IP created by it must first be deleted from the design. Click **OK** to continue. +Confirm that the settings meet your design requirements. It should be noted that while it is possible to change these settings manually later (for example, by manually adding an AXI INTC IP and connecting it to the processor), the easiest way to do so will be to clear the Microblaze processor out of your block design and restart the process of adding the processor. This is to say, the settings chosen here are important. Getting them right the first time will save you time in the long run.
-</WRAP> <WRAP column half> +
-{{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-14.png?600 |}} +
-</WRAP> </WRAP> +
-----+
  
---> Connect the MIG to the Processor (DDR Designs Only) #+**Important!** When working with multiple clocks in a design (as happens to always be the case when working with the MIG) it is important to verify that you are picking the correct //Clock Connection// from the dropdown. In the screenshot to the right, the 100 MHz clk_out1 from a clocking wizard is chosen. You may instead wish to run your design off of ui_clk itself. Do not select the system clock input to the MIG.
  
-<WRAP group> <WRAP column half> +Click **OK** to continue.
-With Block Automation complete, click **Run Connection Automation**.+
 </WRAP> <WRAP column half> </WRAP> <WRAP column half>
-{{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-15.png?600 |}}+{{ :programmable-logic:guides:block-automation.png?600 |}}
 </WRAP> </WRAP> </WRAP> </WRAP>
 ---- ----
-<WRAP group> <WRAP column half> +Next, the MIG's AXI interface must be connected to Microblaze's cache ports, in order to allow data to move back and forth between processor and DDR memory.
-In the dialog that pops up, select **ONLY** the S_AXI interface from the list of interfaces to connect. Click **OK**, and Vivado will automatically connect the MIG to the Microblaze processor via the processor's IC and DC (instruction and data cache) interfaces.+
  
-**Note:** //Selecting all three interfaces may result in incorrect connections. The IC and DC interfaces are specified to be connected to the S_AXI interface from within the automation options for S_AXI.// +{{section>microblaze-adding-ddr#connect_the_mig_to_the_microblaze_processor}}
-</WRAP> <WRAP column half> +
-{{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-16.png?600 |}} +
-</WRAP> </WRAP> +
----- +
-<WRAP group> <WRAP column half> +
-Side note, the //View// dropdown in the top right corner of Vivado's Diagram pane can be used to reduce the amount of visual clutter in the diagram, and help to quickly spot problems. For example, the //Interfaces View// presents only the complex interfaces in the design, and helps in verifying that AXI peripherals are connected to the processor through the DP port, and that the MIG is connected through the IC and DC ports. +
- +
-Importantly, this view does not show you any clock, reset, or interrupt connections. If you take a look at this view, make sure to switch back to the //Default View// before continuing this guide. +
-</WRAP> <WRAP column half> +
-{{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-17.png?600 |}} +
-</WRAP> </WRAP> +
- +
-<--+
 ---- ----
 <WRAP group> <WRAP column half> <WRAP group> <WRAP column half>
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 {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-20.png?600 |}} {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-20.png?600 |}}
 </WRAP> </WRAP> </WRAP> </WRAP>
 +</WRAP>
 +<--
 ---- ----