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programmable-logic:guides:getting-started-with-vivado [2022/10/03 15:28] – [Prerequisites] unrelevantprogrammable-logic:guides:getting-started-with-vivado [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 +~~TechArticle~~
 +====== Getting Started with Vivado for Hardware-Only Designs ======
 +===== Introduction =====
  
 +{{ learn/programmable-logic/tutorials/2020.1/create-vivado-project/create_project.png?direct&500 |The Vivado Start Page}}
 +
 +The goal of this guide is to familiarize the reader with the Vivado tools through the "Hello World!" of hardware, blinking an LED.
 +
 +**Note:** //While this guide was originally created using Vivado 2016.4, the workflow described has not substantially changed, and the guide works as described through to Vivado 2020.1, the latest version as of time of writing.//
 +
 +----
 +===== Prerequisites =====
 +Prior to starting this guide make sure to install Vivado:
 +  * For versions 2019.2 and later, see [[vivado:installing-vivado:v2019.2]].
 +  * For versions prior to 2019.2, see [[vivado:installing-vivado:start]].
 +
 +----
 +===== Guide =====
 +
 +{{page>programmable-logic:guides:vivado-launch&showheader}}
 +
 +{{page>programmable-logic:guides:vivado-new-project&showheader}}
 +
 +==== The Flow Navigator ====
 +<WRAP group>
 +<WRAP column half>
 +The //Flow Navigator// is the most important pane of the main Vivado window to know. It is how a user navigates between different tools within Vivado.
 +
 +The Navigator is broken into seven sections:
 +  * //Project Manager//
 +    * Access project settings, add new source files, view snippets of useful RTL code, and add components of a hardware design (IP) included within the tool to your own design.
 +  * //IP Integrator//
 +    * Create a hardware design through the use of a Block Design by connecting IP blocks together.
 +  * //Simulation//
 +    * Debug and verify a hardware design fully within software, without deploying it to hardware.
 +  * //RTL Analysis//
 +    * See how the tools are interpreting a design by viewing the circuit that the design describes.
 +  * //Synthesis//
 +    * Modify Synthesis settings and view post-synthesis reports - determine whether the design meets timing, and how much of the chip resources it will use.
 +  * //Implementation//
 +    * Modify Implementation settings and view post-implementation reports - determine whether the design meets timing, and how much of the chip resources it will use.
 +  * //Program and Debug//
 +    * Access to settings for bitstream generation and the Hardware Manager. Used to build a design and deploy it to a board.
 +</WRAP>
 +<WRAP column half>
 +{{ vivado:getting_started:flownav.png?direct&200 |}}
 +</WRAP>
 +</WRAP>
 +
 +----
 +==== The Project Manager ====
 +
 +<WRAP group>
 +<WRAP column half>
 +This tool is where most development will occur and is the initial tool open after creating a new project.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started:v2016.4:project-manager:project-manager.png?direct&600 |}}
 +</WRAP>
 +</WRAP>
 +----
 +<WRAP group>
 +<WRAP column half>
 +The //Project Manager// consists of four panes, //Sources//, //Properties//, //Results//, and the //Workspace//.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started:v2016.4:project-manager:project-manager-explained.png?direct&600 |}}
 +</WRAP>
 +</WRAP>
 +----
 +<WRAP group>
 +<WRAP column half>
 +The //Sources// pane contains the project hierarchy and is used for opening up files. The folder structure is organized such that the HDL files are kept under the //Design Sources// folder, constraints are kept under the //Constraints// folder, and simulation files are kept under the //Simulation Sources// folder. Files can be opened in the Workspace by double-clicking on the corresponding entry in the Sources pane. Sources can also be added by either right clicking the folder to add the file to and selecting //Add Sources// or by clicking the //Add Sources// button ({{:vivado:getting_started:add_sources_btn.png?nolink}}).
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started:v2016.4:project-manager:sources-pane.png?direct&400 |}}
 +</WRAP>
 +</WRAP>
 +----
 +<WRAP group>
 +<WRAP column half>
 +The //Properties// pane allows for viewing and editing of file properties. When a file is selected in the Sources pane its properties are shown in here. This pane can usually be ignored.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started:v2016.4:project-manager:properties-pane.png?direct&400 |}}
 +</WRAP>
 +</WRAP>
 +----
 +<WRAP group>
 +<WRAP column half>
 +The unnamed pane at the bottom of the Project Manager window consists of several different useful tools for debugging a project. The most important one to know is the //Messages// tool. This tool parses the Tcl console for errors, warnings, and other important information and displays it in an informative way.
 +
 +These tools can be accessed by selecting the different tabs at the bottom of this pane.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started:v2016.4:project-manager:results-pane.png?direct&600 |}}
 +</WRAP>
 +</WRAP>
 +----
 +<WRAP group>
 +<WRAP column half>
 +The //Tcl Console// is a tool that allows for running commands directly without the use of the main user interface. Some messages may link to the Tcl Console to provide more information regarding an error.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started:v2016.4:project-manager:tcl-console-tab.png?direct&600 |}}
 +</WRAP>
 +</WRAP>
 +----
 +<WRAP group>
 +<WRAP column half>
 +The //Reports// tool is useful for quickly jumping to any one of the many reports that Vivado generates on a design. These reports include power, timing, and utilization just to name a few.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started:v2016.4:project-manager:reports-tab.png?direct&600 |}}
 +</WRAP>
 +</WRAP>
 +----
 +<WRAP group>
 +<WRAP column half>
 +The //Log// displays the output from the latest Synthesis, Implementation, and Simulation runs. Digging into this is usually not necessary as the reports and messages view store the information in the log in a more readable format.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started:v2016.4:project-manager:log-tab.png?direct&600 |}}
 +</WRAP>
 +</WRAP>
 +----
 +<WRAP group>
 +<WRAP column half>
 +The last tool is the //Design Runs//. Using this tool run settings can be edited and new runs can be created. This tool is useful when targeting multiple devices with the same design.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started:v2016.4:project-manager:design-runs-tab.png?direct&600 |}}
 +</WRAP>
 +</WRAP>
 +----
 +<WRAP group>
 +<WRAP column half>
 +The most important pane in the Project Manager is the //Workspace//. The Workspace is where reports are opened for viewing and HDL/constraints files are opened for editing. Initially the Workspace displays the //Project Summary// which show some basic information from some of the reports.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started:v2016.4:project-manager:workspace-pane.png?direct&600 |}}
 +</WRAP>
 +</WRAP>
 +
 +----
 +==== Adding a Constraint File ====
 +
 +Constraint files describe the requirements put upon a design by the components surrounding an FPGA - including all peripherals, external clocks, and more.
 +
 +In order to connect the ports found in an RTL top module (described later) with the physical pins of the FPGA, a constraint file needs to be added or created. Digilent provides Xilinx Design Constraint (XDC) files for each board. Download [[https://github.com/Digilent/digilent-xdc/archive/master.zip|digilent-xdc-master.zip]], the ZIP Archive containing each of these master XDC files, then extract it in a location you will remember.
 +
 +<WRAP group>
 +<WRAP column half>
 +In the //Project Manager// section of the //Flow Navigator//, click the {{:vivado:getting_started:v2016.4:sources:add-sources.png}} button. In the wizard that pops up, select //Add or create constraints// then click //Next//.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started:v2016.4:sources:add-constr-1.png?direct&500 |}}
 +</WRAP>
 +</WRAP>
 +----
 +<WRAP group>
 +<WRAP column half>
 +At this stage, Vivado provides a list of all of the constraint files that will be added or created when we click Finish. Currently this list is empty, this will change when files have been added or created. A constraint file will not be created from scratch in this guide, so click //Add Files//.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started:v2016.4:sources:add-constr-2.png?direct&500 |}}
 +</WRAP>
 +</WRAP>
 +----
 +<WRAP group>
 +<WRAP column half>
 +Find the directory you extracted the //digilent-xdc-master.zip// archive into, then click on the file for your board. This should add the name of the file to the //File Name// field.
 +
 +Click //OK// to continue.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started:v2016.4:sources:add-constr-3.png?direct&500 |}}
 +</WRAP>
 +</WRAP>
 +----
 +<WRAP group>
 +<WRAP column half>
 +Make sure that the selected XDC file has been added into the list of sources, and that the //Copy constraint files into project// is checked, then click //Finish//.
 +
 +**Note:** //Leaving the Copy... box unchecked means that any editing done to the constraint file will be reflected in the original copy. Checking the box is highly recommended//
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started:v2016.4:sources:add-constr-4.png?direct&500 |}}
 +</WRAP>
 +</WRAP>
 +----
 +<WRAP group>
 +<WRAP column half>
 +In the //Sources// pane of the //Project Manager//, expand the //Constraints// folder, then double click on the XDC file you just added. Each of Digilent's XDC files contains constraints for each of the commonly used peripherals on their respective boards. For this demo, constraining the default system clock and a single led is required.
 +
 +Find and uncomment the lines that call //get_ports// on the names led[0] and clk by removing the '#' symbol at the beginning of the line. On some boards the clock port will consist of two different ports, clk_p and clk_n. The clock port is occasionally named something like sysclk, but always appears at the top of the XDC file. Uncomment the //create_clock// line that follows the clock port/s definition as well.
 +
 +**Note:** //A board using clk_p/clk_n pins means that the input clock that uses differential logic. If you want to know more, read this article on [[wp>low-voltage differential signalling]].//
 +
 +Change the name inside of the get_ports call to 'led' from 'led[0]'. Do the same for the clock if it is named something other than 'clk' or 'clk_p' and 'clk_n'.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started:v2016.4:edit-constraints.png?direct&500 |}}
 +</WRAP>
 +</WRAP>
 +
 +----
 +==== Creating a Verilog Source File ====
 +
 +Verilog is one of several hardware description languages (HDLs) that can be used within Vivado to describe a circuit to be implemented within an FPGA. This section describes how to create a Verilog file within Vivado, and create a simple circuit that will work on any Digilent FPGA development board.
 +
 +<WRAP group>
 +<WRAP column half>
 +In the //Project Manager// section of the //Flow Navigator//, click the {{:vivado:getting_started:v2016.4:sources:add-sources.png}} button again. Select //Add or create design sources// then click //Next//.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started:v2016.4:sources:create-source-1.png?direct&500 |}}
 +</WRAP>
 +</WRAP>
 +----
 +<WRAP group>
 +<WRAP column half>
 +As before, at this stage, we will be provided a list of all of the source files that will be added or created when we click Finish. Instead of clicking Add Files, click //Create File//.
 +
 +**Note:** //It is also possible to add existing source files in the same way the constraint file was added, above.//
 +
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started:v2016.4:sources:create-source-2.png?direct&500 |}}
 +</WRAP>
 +</WRAP>
 +----
 +<WRAP group>
 +<WRAP column half>
 +You will be prompted to select a //File type//, //File name//, and //File location//. Make sure to pick //Verilog// and //<Local to project>// for the type and location. Give your file a name ending in '.v'.
 +
 +**Important:** //Do NOT use spaces in your file name. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]].//
 +
 +Click //OK// to continue.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started:v2016.4:sources:create-source-3.png?direct&500 |}}
 +</WRAP>
 +</WRAP>
 +----
 +<WRAP group>
 +<WRAP column half>
 +Make sure that the new Verilog source file has been added into the list of sources, then click //Finish//.
 +</WRAP>
 +<WRAP column half>
 +{{ :vivado:getting_started:v2016.4:sources:create-source-4.png?direct&500 |}}
 +</WRAP>
 +</WRAP>
 +----
 +
 +Unlike when the constraint file was added, at this point a //Define Module// dialog will pop up. You can rename your Verilog module using the //Module name// field, but this is unnecessary. The Verilog module's clock and led ports need to be defined. Clicking the //Add// ({{:vivado:getting_started:v2016.4:sources:add-port.png?direct|}}) button will add an empty slot for a port to the //I/O Port Definitions// list.
 +
 +{{ :vivado:getting_started:v2016.4:sources:define-module-clk.png?direct&500 |}}
 +
 +There are five fields to define for each of the module's I/O ports:
 +  * **Port Name:** This field defines the name of the port and needs to match one of the names you used in your XDC file.
 +  * **Direction:** This drop-down menu can be set to //input//, //output//, or //inout//, defining the direction that signals propagate through this port, with respect to your module. Outputs are the signals that your module will be controlling.
 +  * **Bus:** This can be checked or not, when checked, this port consists of multiple single bit signals, grouped into a single bus.
 +  * **MSB:** The index of the most significant bit of the port, if it is a bus. This option is grayed out for single-bit ports.
 +  * **LSB:** The index of the least significant bit of the port, if it is a bus. This option is grayed out for single-bit ports.
 +
 +**Note:** //If you are defining a module which will be instantiated in another module, which we will not go into in this guide, be aware that the port names of non-"top" modules should not be declared in the XDC.//
 +
 +If your board uses differential clocking, add two single-bit input ports with the same names as the positive and negative clock ports that were uncommented in your XDC file. Otherwise, add a single single-bit input port with the same name as the clock port that was uncommented in your XDC file.
 +
 +Add a single-bit output port with the same name as the LED port that was uncommented in your XDC file.
 +
 +Once these two or three ports have been added, click //OK// to continue.
 +----
 +At this point, the new source file will be added to the //Design Sources// folder in the //Sources// pane of the //Project Manager//. Expand this folder and double click on the file to open it.
 +
 +Next, some Verilog code needs to be written to define how the design will actually behave.
 +
 +{{ :vivado:getting_started:v2016.4:sources:edit-source.png?direct&800 |}}
 +
 +Between the ');' that comes after the module's port list and the 'endmodule' statement, add the following lines of code.
 +
 +This snippet of code implements a 25 bit counter, which will increment by 1 every clock cycle, and roll back over to 0 after ~33 million cycles (about a third of a second, given a 100MHz input clock). The LED is directly driven by the top bit of the counter, which, of the bits, changes the least frequently. Given a 100MHz clock, the LED will blink (go through a full cycle of low-to-high-to-low transitions) approximately three times per second.
 +
 +<code verilog>
 +reg [24:0] count = 0;
 +
 +assign led = count[24];
 +
 +always @ (posedge(clk)) count <= count + 1;
 +</code>
 +
 +If your board is differentially clocked, add the following lines of code after ');' and before the 'reg [24:0] count = 0;' line.
 +
 +This instantiates a differential input buffer, which will allow you to get a non-differential clock which can be used to clock the FPGA fabric.
 +
 +<code verilog>
 +wire clk;
 +
 +IBUFGDS clk_inst (
 +    .O(clk),
 +    .I(clk_p),
 +    .IB(clk_n)
 +);
 +</code>
 +
 +It should be noted that the rate at which the clock will blink will differ depending on the board used. System clocks on different Digilent boards run at a number of different rates, depending on the needs of the board. The system clock period in nanoseconds can be found on the //create_clock// line of the XDC file.
 +
 +After completing this guide, it is suggested to try changing the provided Verilog code so that the clock blinks at 1 Hertz. (Note that the XDC file only //describes// the period of the input clock, and changing it will only misinform the tools, rather than changing the input clock period)
 +
 +----
 +==== Generate a Bitstream ====
 +
 +In order to create a file that can be used to program the target board, each stage of the "compilation pipeline" needs to be run.
 +
 +This starts with //Synthesis//. Synthesis creates a description of the logic gates and connections between them required to perform the functionality described by the HDL files, given the constraints included in XDC files. To run Synthesis click either {{:vivado:getting_started:synth_ico.png?nolink}} in the toolbar or {{:vivado:getting_started:synth_btn.png?nolink}} in the //Flow Navigator//. The output of Synthesis is then passed to Implementation.
 +
 +//Implementation// has several steps. The steps that are always run are //Opt Design// (Optimize the design to fit on the target FPGA), //Place Design// (Lay out the design in the target FPGA fabric), and //Route Design// (Route signals through the fabric). To run Implementation click either {{:vivado:getting_started:impl_ico.png?nolink}} in the toolbar or {{:vivado:getting_started:impl_btn.png?nolink}} in the //Flow Navigator//. This output is then passed on to the Bitstream Generator.
 +
 +The //Bitstream Generator// generates the final output file needed for programming the FPGA. To run Bitstream Generation click either {{:vivado:getting_started:gen_bit_ico.png?nolink}} in the toolbar or {{:vivado:getting_started:gen_bit_btn.png?nolink}} in the //Flow Navigator//. With no settings changed, the generator will create a '.bit' file.
 +
 +Depending on the complexity of the design, the board used, and the strength of your computer, the process of building the project can take between 5 and 60 minutes. When complete, a pop up dialog will appear, prompting you to select one of several options. None are relevant for the purposes of this guide, so click **Cancel**. The "write_bitstream complete" status message can be seen in the top right corner of the window, indicating that the demo is ready to be deployed to your board.
 +
 +----
 +===== =====
 +{{page>programmable-logic:guides:vivado-hardware-manager&showheader}}
 +
 +==== In Conclusion ====
 +
 +You should now see one of the LEDs on your board blinking!
 +
 +Be sure to visit your board's resource center for more tutorials and demo projects. A link to each resource center can be found on this wiki's [[programmable-logic:start]] page.
 +
 +/*{{tag>learn programmable-logic software tutorial vivado arty arty-a7 arty-s7 arty-z7 basys-3 cmod-a7 cmod-s7 cora-z7 genesys-2 nexys-4-ddr nexys-a7 nexys-video zybo-z7 zybo zedboard sword }}*/