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programmable-logic:genesys:start [2022/09/08 13:46] – changed forum.digilentinc.com to forum.digilent.com jeff.greenberg_ni.comprogrammable-logic:genesys:start [2022/10/04 04:38] (current) – external edit 127.0.0.1
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 +~~NOTOC~~ 
 +     
 +====== Genesys ======
 +{{Digilent Infobox
 +| Manual = [[reference-manual]]
 +| Support = https://forum.digilentinc.com/forum/4-fpga/
 +| Title = Genesys
 +| Subtitle = Virtex-5 FPGA Development Board 
 +| Header = Features
 +| Bullet = Multiple USB2 ports for programming, data transfer, and hosting applications 
 +| Header = Key Specifications
 +| Memory = 16Mbyte StrataFlash™ for \\ configuration and data storage
 +| Logic Cells =  7,200 slices (4 LUTs and 8 flip-flops)
 +| Block RAM = 1.7Mbits
 +| DCM = 12
 +| PLL = 6
 +| DSP = 48 slices
 +| Internal clock = 500MHz+
 +| DDR2 = 256MB DDR2 SODIMM with \\ 64-bit wide data
 +| Ethernet = 10/100/100 PHY and \\ RS-232 serial port
 +| Header = Connectivity and On-board I/O
 +| HDMI = Up to 1600x1200 and 24-bit color
 +| Audio = AC-97 Codec with line-in, \\ line-out, and headphone
 +| Pmod Connectors = 4
 +| Connectors = 112 I/Os routed \\ to expansion connectors
 +| Switches = 1 2-axis navigation switch \\ 8 slide switches
 +| LCD = 16x2 character
 +| Buttons = 2
 +| LEDs = 8
 +| Header = Electrical
 +| Power = 5V external (2.1mm coaxial) supply
 +| Logic Level = 3.3V
 +| Header = Physical
 +| Width = x in
 +| Length = y in
 +| Header = Design Resources
 +| Master UCF = {{:reference:programmable-logic:genesys:genesysgeneral.zip|ZIP}}
 +| EDK BSB Files = {{:reference:programmable-logic:genesys:genesys_bsb_support_v1_4.zip|ZIP}}
 +| VHDCI Plug = {{:reference:programmable-logic:genesys:genesys-vhdci-datasheet.pdf| PDF}}
 +| VHDCI Receptacle = {{:reference:programmable-logic:genesys:genesys-vhdci-receptacle-datasheet.pdf| PDF}}
 +| Header = Documentation
 +| Primary IC = [[https://docs.xilinx.com/v/u/en-US/ds202| Virtex-5]] (Virtex5-LX50T)
 +| Reference Manual = [[programmable-logic/genesys/reference-manual]]
 +| Schematic = {{:reference:programmable-logic:genesys:genesys_sch.pdf|Rev. C}}
 +}}
  
 +{{page>reference-manual}} \\ \\
 + 
 +===== Tutorials =====
 +{{topic>genesys +tutorial}}
 +
 +----
 +===== Example Projects =====
 +{{topic>genesys +project}}
 +
 +----
 +===== Additional Resources =====
 +  * **Ethernet Project** {{:genesys:genesys_lwipdemo.zip|Download}} 
 +    * Ethernet demonstration project (LightWeight IP demonstration project originally for Xilinx ML505 ported to Genesys).
 +  * **Microblaze EDK Demo**{{:genesys:genesys_ip_cores.zip|Download}} 
 +    * This zip file contains an EDK demo project that illustrates how to use the Genesys AC97 codec with Microblaze.
 +  * **EDK BSB Project**{{:genesys:genesys_bsb_design.zip|Download}} 
 +    * Tutorial and example project showing a Genesys-based design, generated with the EDK BSB wizard.
 +  * **EDK and SDK Projects** {{:genesys:genesys_ac97_edk_demo.zip|Download}} 
 +    * A Microblaze based audio demo that demonstrates how to use the AC97 audio codec.
 +  * **Out of Box Demo/Test** {{:genesys:genesys_bist_clean.zip|Download}}
 +    * The source code for the out of box demo and test the exercises all onboard components. This is a very advanced Microblaze project and the source code for it may be difficult to follow, but it is useful to teach advanced users how to use specific components. 
 +
 +----
 +
 +{{tag>programmable-logic programmable-logic-start genesys resource-center}}