Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
programmable-logic:genesys-zu:start [2022/09/12 11:37] – changed forum.digilentinc.com to forum.digilent.com jeff.greenberg_ni.comprogrammable-logic:genesys-zu:start [2022/10/04 04:38] (current) – external edit 127.0.0.1
Line 1: Line 1:
 +~~NOTOC~~ 
  
 +====== Genesys ZU ======
 +{{Digilent Infobox
 +| Store Page = https://digilent.com/shop/genesys-zu-zynq-ultrascale-mpsoc-development-board/
 +| Manual = [[reference-manual]]
 +| Getting Started = [[getting-started]]
 +| Support = https://forum.digilentinc.com/forum/4-fpga/
 +| Title = Genesys ZU
 +| Subtitle = Zynq Ultrascale+ MPSoC Development Board
 +
 +| Header = Features
 +
 +| Header = Key FPGA Specifications
 +| Part Number = XCZU3EG-SFVC784-1-E
 +| Part Number (*) = XCZU5EV-SFVC784-1-E
 +| APU = Quad-core ARM Cortex-A53
 +| RPU = Dual-core ARM Cortex-R5
 +| GPU = ARM Mali™-400
 +| Video Codec = H.264/H.265 (*Only on 5EV variant)
 +| Logic Cells = 154K / (256K*)
 +| Block RAM = 7.6 Mb / (5.1 Mb*)
 +| UltraRAM = 18.0 Mb (*Only on 5EV variant)
 +| DSP Slices = 360 / (1,248*)
 +| Clock Resources = 3 Clock Management Tiles (4*)
 +| Bullet = (*ZU-5EV variant value where different)
 +
 +| Header = Peripheral Connectivity
 +| USB-C = USB Type-C 3.1 Gen1 Dual-Role Device
 +| MiniPCIe / mSATA = dual slot, Half-/Full-size
 +| USB 2.0 Host = 2 x Type-A
 +
 +| Header = Network Connectivity
 +| On-board Wi-Fi = 2.4 <nowiki>GHz</nowiki>
 +| Ethernet = 1G w/ IEEE 1588
 +| WLAN/WWAN/LoRa = option - MiniPCIe
 +| SFP+ 10G Ethernet = (*Only on 5EV variant)
 +| Bullet = (*ZU-5EV variant value where different)
 +
 +| Header = Memories
 +| Main Memory = DDR4, 4GB, 1866 MT/s (2133 MT/s*), upgradeable
 +| Flash = ISSI 256 Mib SNOR
 +| SD = 104 <nowiki>MB</nowiki>/s
 +| SSD = option - mSATA
 +| Bullet = (*ZU-5EV variant value where different)
 +
 +| Header = Multimedia
 +| DisplayPort = 1.2a Dual-Lane
 +| Pcam = 2 x Dual-Lane
 +| HDMI Source = (*Only on 5EV variant)
 +| HDMI Sink = (*Only on 5EV variant)
 +| Audio Codec = Present on both variants
 +| Bullet = (*ZU-5EV variant value where different)
 +
 +| Header = Expansion Connectors
 +| Pmod = 4x
 +| SYZYGY = 1x
 +| FMC = 1x
 +| FMC Gigabit = 1x (*Only on 5EV variant)
 +| Bullet = (*ZU-5EV variant value where different)
 +
 +| Header = User I/O
 +| LEDs = 4 PL-connected LEDs \\ 1 MIO-connected <nowiki>LED</nowiki>
 +| RGB LED = 1 PL-connected RGB <nowiki>LED</nowiki>
 +| Buttons = 5 PL-connected buttons \\ 2 MIO-connected buttons
 +| Switches = 4 PL-connected switches
 +
 +| Header = Product Compliance
 +| HTC = 8471500150
 +| ECCN = 5A992
 +}}
 +
 +The Digilent Genesys ZU is a stand-alone Zynq UltraScale+ MPSoC development board. It is an advanced computing platform with powerful multimedia and network connectivity interfaces. The excellent mix of on-board peripherals, upgrade-friendly DDR4, Mini PCIe and microSD slots, and high-speed expansion connectors are bound to support a wide number of use-cases. Furthermore, the Genesys ZU is available in two variants with different MPSoC options and additional features for even more flexibility.
 +
 +The Xilinx Zynq UltraScale+ MPSoC at the heart of the Genesys ZU is a big leap from the Zynq-7000 series. Faster and more processor cores, upgraded memory interface, integrated gigabit transceivers bring support for DDR4, USB Type-C 3.1, PCIe, SATA, DisplayPort, SFP+* and HDMI*. 
 +The Genesys ZU is primarily targeted towards Linux-based applications that allows easy access to Wi-Fi, cellular radio (WWAN), <nowiki>SSD</nowiki>, USB SuperSpeed, and 4K video.
 +
 +{{Digilent Image Gallery 
 +| image = {{ :reference:programmable-logic:genesys-zu:genesyszu-obl-2000.png?direct |}}
 +| image = {{ :reference:programmable-logic:genesys-zu:genesyszu-top-2000.png?direct |}}
 +| image = {{ :reference:programmable-logic:genesys-zu:genesyszu-bottom-2000.png?direct |}}
 +}}
 +
 +===== Getting Started =====
 +  * [[getting-started|]]
 +
 +----
 +===== Documentation =====
 +
 +  * [[programmable-logic:genesys-zu:reference-manual]]
 +  * [[https://github.com/Digilent/digilent-xdc|Master XDC Files for Digilent Boards]]
 +  * [[https://github.com/Digilent/vivado-boards|Board Files for Digilent Boards]]
 +  * {{ :reference:programmable-logic:genesys-zu:genesys_zu-3eg_sch_public.pdf |Genesys ZU-3EG Schematic Rev B.1}}
 +  * {{ :reference::programmable-logic:genesys-zu:genesys_zu-3eg_revd1_sch_public.pdf |Genesys ZU-3EG Schematic Rev D.1}}
 +  * {{ :reference::programmable-logic:genesys-zu:genesys_zu-5ev_sch_public.pdf |Genesys ZU-5EV Schematic Rev D.1}}
 +  * [[https://docs.xilinx.com/v/u/en-US/ds890-ultrascale-overview|Xilinx Ultrascale Architecture and Product Data Sheet: Overview]]
 +
 +----
 +===== Guides =====
 +  * [[programmable-logic/guides/installing-vivado-and-vitis]]
 +    * **Note:** //When installing Vivado, make sure to include support for Zynq Ultrascale+ parts.//
 +  * [[programmable-logic/guides/getting-started-with-ipi]]
 +    * **Note:** //This guide was originally written for non-Ultrascale Zynq boards and boards using Microblaze. The flow for Ultrascale Zynq is largely the same as non-Ultrascale Zynq. The "Zynq Ultrascale+ MPSoC" IP core should be used in place of the "ZYNQ7 Processing System"//
 +
 +----
 +===== Example Projects =====
 +  * [[programmable-logic:genesys-zu:demos:hello-world|Genesys ZU Hello World Project]]
 +  * [[programmable-logic:genesys-zu:demos:hdmi|Genesys ZU 5EV HDMI Demo Project]]
 +  * [[https://github.com/Digilent/Genesys-ZU-HW/tree/master|Genesys ZU Out-of-Box Vivado Project]]
 +  * [[https://github.com/Digilent/Genesys-ZU-OS|Genesys ZU Out-of-Box Petalinux Project]]
 +
 +----
 +===== Featured Community Projects =====
 +  * [[https://www.hackster.io/adam-taylor/high-performance-imaging-ac156d|High Performance Imaging with Genesys ZU 3EG]]
 +    * Created by Adam Taylor.
 +
 +----
 +===== Additional Resources ===== 
 +
 +  * {{:reference:programmable-logic:genesys-zu:genesys_zu_dimensions.zip| Genesys ZU Mechanical Drawings}}
 +
 +----
 +{{tag>resource-center}}