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| programmable-logic:genesys-zu:start [2021/05/14 16:04] – ↷ Page moved from reference:programmable-logic:genesys-zu:start to programmable-logic:genesys-zu:start Arthur Brown | programmable-logic:genesys-zu:start [2022/10/04 04:38] (current) – external edit 127.0.0.1 | ||
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| ====== Genesys ZU ====== | ====== Genesys ZU ====== | ||
| {{Digilent Infobox | {{Digilent Infobox | ||
| - | | Store Page = https://store.digilentinc.com/ | + | | Store Page = https://digilent.com/shop/ |
| | Manual = [[reference-manual]] | | Manual = [[reference-manual]] | ||
| | Getting Started = [[getting-started]] | | Getting Started = [[getting-started]] | ||
| Line 14: | Line 14: | ||
| | Header = Key FPGA Specifications | | Header = Key FPGA Specifications | ||
| | Part Number = XCZU3EG-SFVC784-1-E | | Part Number = XCZU3EG-SFVC784-1-E | ||
| + | | Part Number (*) = XCZU5EV-SFVC784-1-E | ||
| | APU = Quad-core ARM Cortex-A53 | | APU = Quad-core ARM Cortex-A53 | ||
| | RPU = Dual-core ARM Cortex-R5 | | RPU = Dual-core ARM Cortex-R5 | ||
| Line 67: | Line 68: | ||
| | Header = Product Compliance | | Header = Product Compliance | ||
| | HTC = 8471500150 | | HTC = 8471500150 | ||
| - | | ECCN = 5A002.a.4 | + | | ECCN = 5A992 |
| }} | }} | ||
| Line 87: | Line 88: | ||
| ===== Documentation ===== | ===== Documentation ===== | ||
| - | * [[reference:programmable-logic: | + | * [[programmable-logic: |
| * [[https:// | * [[https:// | ||
| * [[https:// | * [[https:// | ||
| - | * {{ : | + | * {{ : |
| - | * [[https://www.xilinx.com/ | + | * {{ : |
| + | * {{ : | ||
| + | * [[https://docs.xilinx.com/ | ||
| ---- | ---- | ||
| ===== Guides ===== | ===== Guides ===== | ||
| - | * [[vivado:installing-vivado:start|]] | + | * [[programmable-logic/ |
| * **Note:** //When installing Vivado, make sure to include support for Zynq Ultrascale+ parts.// | * **Note:** //When installing Vivado, make sure to include support for Zynq Ultrascale+ parts.// | ||
| - | * **Note:** //Digilent projects for the Genesys ZU are currently only supported in Vivado 2019.1.// | + | |
| - | * [[vivado:getting-started-with-ipi:start|]] | + | |
| * **Note:** //This guide was originally written for non-Ultrascale Zynq boards and boards using Microblaze. The flow for Ultrascale Zynq is largely the same as non-Ultrascale Zynq. The "Zynq Ultrascale+ MPSoC" IP core should be used in place of the "ZYNQ7 Processing System"// | * **Note:** //This guide was originally written for non-Ultrascale Zynq boards and boards using Microblaze. The flow for Ultrascale Zynq is largely the same as non-Ultrascale Zynq. The "Zynq Ultrascale+ MPSoC" IP core should be used in place of the "ZYNQ7 Processing System"// | ||
| ---- | ---- | ||
| - | ===== Out-of-Box Demo ===== | + | ===== Example Projects |
| - | + | * [[programmable-logic: | |
| - | * [[https:// | + | * [[programmable-logic: |
| - | * [[https:// | + | * [[https:// |
| + | * [[https:// | ||
| ---- | ---- | ||

