Differences

This shows you the differences between two versions of the page.

Link to this comparison view

programmable-logic:genesys-zu:reference-manual [2022/03/28 20:23] – Update xilinx links Arthur Brownprogrammable-logic:genesys-zu:reference-manual [2022/10/04 11:38] (current) – external edit 127.0.0.1
Line 371: Line 371:
   - Turn the board on. The board will now boot the image on the microSD card.   - Turn the board on. The board will now boot the image on the microSD card.
  
-For more details about SD boot mode see "SD Boot Mode" section in [[https://docs.xilinx.com/r/en-US/ug1137-zynq-ultrascale-mpsoc-swdev|Zynq UltraScale+ MPSoC Software Developer Guide (UG1137]]).+For more details about SD boot mode see "SD Boot Mode" section in [[https://docs.xilinx.com/v/u/2020.1-English/ug1137-zynq-ultrascale-mpsoc-swdev|Zynq UltraScale+ MPSoC Software Developer Guide (UG1137]]).
  
 ==== 2.3 Quad SPI Boot Mode ==== ==== 2.3 Quad SPI Boot Mode ====
Line 380: Line 380:
   - Turn the board on. The board will now boot the image stored in the Quad SPI flash.   - Turn the board on. The board will now boot the image stored in the Quad SPI flash.
  
-For more details about Quad SPI boot mode see "QSPI24 and QSPI32 Boot Modes" section in [[https://docs.xilinx.com/r/en-US/ug1137-zynq-ultrascale-mpsoc-swdev|Zynq UltraScale+ MPSoC Software Developer Guide (UG1137]]).+For more details about Quad SPI boot mode see "QSPI24 and QSPI32 Boot Modes" section in [[https://docs.xilinx.com/v/u/2020.1-English/ug1137-zynq-ultrascale-mpsoc-swdev|Zynq UltraScale+ MPSoC Software Developer Guide (UG1137]]).
  
 ==== 2.4 USB Boot Mode ==== ==== 2.4 USB Boot Mode ====
  
-It is the only boot mode apart from JTAG where the MPSoC takes a slave role. It shows up as a DFU (Device Firmware Upgrade) USB device to the PC, waiting for a configuration. Using this boot mode you will be able to load the newly created image on Zynq UltraScale+ via the USB Port. For more details see the "Boot Sequence for USB Boot Mode" mode in [[https://docs.xilinx.com/v/u/2019.1-English/ug1209-embedded-design-tutorial|Zynq UltraScale+ MPSoC: Embedded Design Tutorial (UG1209)]].+It is the only boot mode apart from JTAG where the MPSoC takes a slave role. It shows up as a DFU (Device Firmware Upgrade) USB device to the PC, waiting for a configuration. Using this boot mode you will be able to load the newly created image on Zynq UltraScale+ via the USB Port. For more details see the "Boot Sequence for USB Boot Mode" mode in [[https://docs.xilinx.com/v/u/2020.1-English/ug1209-embedded-design-tutorial|Zynq UltraScale+ MPSoC: Embedded Design Tutorial (UG1209)]].
  
 ==== 2.5 Status LEDs ==== ==== 2.5 Status LEDs ====
Line 645: Line 645:
 ==== 9.2 HDMI Source* ==== ==== 9.2 HDMI Source* ====
  
-The PL side of the Genesys ZU-5EV ZynqUltrascale+ can forward the incoming video and audio streams to the PHY layer via [[https://docs.xilinx.com/r/en-US/pg235-v-hdmi-tx-ss|HDMI 1.4/2.0 Transmitter Subsystem]] from Xilinx. The subsystem bundles a collection of HDMI TX-related IP sub-cores and outputs them as a single IP, providing an out-of-the-box ready-to-use HMDI system. For better performance and quality, the subsystem can be configured through the [[https://docs.xilinx.com/v/u/2019.2-English/ug893-vivado-ide|Vivado®Integrated Design Environment (IDE)]].+The PL side of the Genesys ZU-5EV ZynqUltrascale+ can forward the incoming video and audio streams to the PHY layer via [[https://docs.xilinx.com/r/3.1-English/pg235-v-hdmi-tx-ss|HDMI 1.4/2.0 Transmitter Subsystem]] from Xilinx. The subsystem bundles a collection of HDMI TX-related IP sub-cores and outputs them as a single IP, providing an out-of-the-box ready-to-use HMDI system. For better performance and quality, the subsystem can be configured through the [[https://docs.xilinx.com/v/u/2020.1-English/ug893-vivado-ide|Vivado®Integrated Design Environment (IDE)]].
 The Genesys ZU-5EV board provides a <wrap hi>High-Definition Multimedia Interface (HDMI™)* video output using a TI SN65DP159RGZR HDMI retimer at IC41*</wrap>, on a receptacle at J23. This device is a dual-mode DisplayPort to transition-minimized differential signal (TMDS) retimer supporting digital video interface (DVI) 1.0 and HDMI 1.4b and 2.0 output signals. The device supports data rates up to 6 Gb/s per data lane to support Ultra HD (4K x 2K / 60 Hz) 8-bits per color high-resolution video and HDTV with 16-bit color depth at 1080p (1920 x 1080 / 60 Hz). A convenient characteristic is its ability to automatically configure itself as a redriver at data rates <1 Gb/s, or as a retimer at more than this data rate. This feature can be turned off through I2C programming. The SN65DP159RGZR HDMI retimer data inputs are wired to <wrap hi>GTH Quad 224*</wrap>. The necessary logic for properly interfacing the HDMI Tx Subsystem media access control and the serial transceiver is incorporated by the [[https://docs.xilinx.com/r/en-US/pg230-vid-phy-controller|Video PHY Controller IP]] from Xilinx. The core enables simple connectivity for each TX path, together with some domain-specific configurability. The HDMI video transmit and receive block diagram is shown below, where the Video Phy Controller and the HDMI Transmit Subsystem are bundled as IP-sub cores by the HDMI Subsystem. The Genesys ZU-5EV board provides a <wrap hi>High-Definition Multimedia Interface (HDMI™)* video output using a TI SN65DP159RGZR HDMI retimer at IC41*</wrap>, on a receptacle at J23. This device is a dual-mode DisplayPort to transition-minimized differential signal (TMDS) retimer supporting digital video interface (DVI) 1.0 and HDMI 1.4b and 2.0 output signals. The device supports data rates up to 6 Gb/s per data lane to support Ultra HD (4K x 2K / 60 Hz) 8-bits per color high-resolution video and HDTV with 16-bit color depth at 1080p (1920 x 1080 / 60 Hz). A convenient characteristic is its ability to automatically configure itself as a redriver at data rates <1 Gb/s, or as a retimer at more than this data rate. This feature can be turned off through I2C programming. The SN65DP159RGZR HDMI retimer data inputs are wired to <wrap hi>GTH Quad 224*</wrap>. The necessary logic for properly interfacing the HDMI Tx Subsystem media access control and the serial transceiver is incorporated by the [[https://docs.xilinx.com/r/en-US/pg230-vid-phy-controller|Video PHY Controller IP]] from Xilinx. The core enables simple connectivity for each TX path, together with some domain-specific configurability. The HDMI video transmit and receive block diagram is shown below, where the Video Phy Controller and the HDMI Transmit Subsystem are bundled as IP-sub cores by the HDMI Subsystem.
 {{ :reference:programmable-logic:genesys-zu:gzu_5ev_hdmi_diagram.jpg |}} {{ :reference:programmable-logic:genesys-zu:gzu_5ev_hdmi_diagram.jpg |}}
Line 695: Line 695:
 ==== 9.3 HDMI Sink* ==== ==== 9.3 HDMI Sink* ====
  
-The received video and audio streams can be decoded and properly interfaced with PHY layers via [[https://docs.xilinx.com/r/3.1-English/pg236-v-hdmi-rx-ss|HDMI 1.4/2.0 Receiver Subsystem]] on the PL side of the Genesys ZU-5EV ZynqUltrascale+. The subsystem is a soft IP incorporating all the necessary functionalities through a collection of HDMI RX-related IP sub-cores. For better performance and quality, the subsystem can be configured through [[https://docs.xilinx.com/v/u/2019.2-English/ug893-vivado-ide|Vivado®Integrated Design Environment (IDE)]]. The Genesys ZU-5EV board accepts <wrap hi>HDMI video input on the 19 pin edge connector with shield at J26*</wrap>. All the TMDS RX signals are connected to <wrap hi>TMDS181IRGZT retimer*</wrap>. This device supports four TMDS channels, an audio return channel, and digital control interfaces together with signaling rates up to 6 Gbps+The received video and audio streams can be decoded and properly interfaced with PHY layers via [[https://docs.xilinx.com/r/3.1-English/pg236-v-hdmi-rx-ss|HDMI 1.4/2.0 Receiver Subsystem]] on the PL side of the Genesys ZU-5EV ZynqUltrascale+. The subsystem is a soft IP incorporating all the necessary functionalities through a collection of HDMI RX-related IP sub-cores. For better performance and quality, the subsystem can be configured through [[https://docs.xilinx.com/v/u/2020.1-English/ug893-vivado-ide|Vivado®Integrated Design Environment (IDE)]]. The Genesys ZU-5EV board accepts <wrap hi>HDMI video input on the 19 pin edge connector with shield at J26*</wrap>. All the TMDS RX signals are connected to <wrap hi>TMDS181IRGZT retimer*</wrap>. This device supports four TMDS channels, an audio return channel, and digital control interfaces together with signaling rates up to 6 Gbps
 to allow for the highest resolutions of 4k2k60p24 bits per pixel and up to WUXGA16-bit color depth or 1080p with higher refresh rates. It will automatically configure itself as a redriver at lower data rates (<1.0 Gbps) or as a retimer above this data rate.  to allow for the highest resolutions of 4k2k60p24 bits per pixel and up to WUXGA16-bit color depth or 1080p with higher refresh rates. It will automatically configure itself as a redriver at lower data rates (<1.0 Gbps) or as a retimer above this data rate. 
 In redriver mode, the device supports HDMI1.4b with data rates up to 3.4 Gbps. In redriver mode, the device supports HDMI1.4b with data rates up to 3.4 Gbps.