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| programmable-logic:genesys-zu:getting-started [2021/11/18 15:40] – Damo Ferenc | programmable-logic:genesys-zu:getting-started [2022/10/04 11:38] (current) – external edit 127.0.0.1 | ||
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| **Note:** //At time of manufacturing, | **Note:** //At time of manufacturing, | ||
| + | |||
| + | **Note:** //Some boards may contain an empty SD card due to a manufacturing error. If after the 4.-th instruction the boot sequence doesn' | ||
| **Note:** //For more information about the board, please check the [[programmable-logic/ | **Note:** //For more information about the board, please check the [[programmable-logic/ | ||
| Line 113: | Line 115: | ||
| * Make sure that the installation includes support for Zynq Ultrascale parts. | * Make sure that the installation includes support for Zynq Ultrascale parts. | ||
| * Petalinux 2020.1: | * Petalinux 2020.1: | ||
| - | * // | + | * // |
| * Github repositories for the Hardware and Software components of the Out-of-Box demo. \\ **Note:** //How to clone these repositories is discussed in further detail below.// | * Github repositories for the Hardware and Software components of the Out-of-Box demo. \\ **Note:** //How to clone these repositories is discussed in further detail below.// | ||
| * [[https:// | * [[https:// | ||
| Line 225: | Line 227: | ||
| Any changes in Vivado to the set of IP connected to the processor over AXI require that the system-user.dtsi file be edited to associate the connected IP with compatible drivers. | Any changes in Vivado to the set of IP connected to the processor over AXI require that the system-user.dtsi file be edited to associate the connected IP with compatible drivers. | ||
| - | Additional information on what can be changed and how can be found in Xilinx' | + | Additional information on what can be changed and how can be found in Xilinx' |
| </ | </ | ||
| {{ : | {{ : | ||

