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| programmable-logic:genesys-2:reference-manual [2022/02/11 16:12] – Add DPTI/DSPI row to demo support table Arthur Brown | programmable-logic:genesys-2:reference-manual [2022/10/04 11:38] (current) – external edit 127.0.0.1 | ||
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| ^ Supported Version of Vivado and SDK ^ 2016.4 | ^ Supported Version of Vivado and SDK ^ 2016.4 | ||
| ^ Supported Features | ^ Supported Features | ||
| - | ^ 8 User Switches | + | ^ 8 User Switches |
| - | ^ 8 User LEDs | No | + | ^ 8 User LEDs |
| - | ^ 6 User Push Buttons | + | ^ 6 User Push Buttons |
| - | ^ 128×32 Monochrome OLED Display | + | ^ 128×32 Monochrome OLED Display |
| - | ^ USB-UART Bridge | + | ^ USB-UART Bridge |
| - | ^ Fully Bonded 400-pin FMC HPC Connector | + | ^ Fully Bonded 400-pin FMC HPC Connector |
| - | ^ Micro SD Card Connector | + | ^ Micro SD Card Connector |
| - | ^ HDMI Sink and HDMI Source | + | ^ HDMI Sink and HDMI Source |
| - | ^ VGA Connector | + | ^ VGA Connector |
| - | ^ Two four-lane DisplayPort Connectors | + | ^ Two four-lane DisplayPort Connectors |
| - | ^ Audio Codec w/ Four 3.5mm Jacks | @#A9E091: Yes | No | + | ^ Audio Codec w/ Four 3.5mm Jacks |
| - | ^ 10/100/1000 Ethernet PHY | + | ^ 10/100/1000 Ethernet PHY | No |
| - | ^ 1 GiB 1800 MT/s DDR3 Memory | + | ^ 1 GiB 1800 MT/s DDR3 Memory |
| - | ^ Serial Flash | + | ^ Serial Flash | No |
| - | ^ Five Pmod Ports | No | + | ^ Five Pmod Ports |
| - | ^ Pmod for XADC Signals | + | ^ Pmod for XADC Signals |
| - | ^ USB HID Host | + | ^ USB HID Host | No |
| - | ^ USB 2.0 Host/ | + | ^ USB 2.0 Host/ |
| - | ^ PC - FPGA Data Transfer Interfaces (DPTI/ | + | ^ PC - FPGA Data Transfer Interfaces (DPTI/ |
| ~~REFNOTES~~ | ~~REFNOTES~~ | ||
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| | 1.5 V | DDR3 and FPGA I/O | IC32: LTC3618 | | 1.5 V | DDR3 and FPGA I/O | IC32: LTC3618 | ||
| | 0.75V | DDR3 termination, | | 0.75V | DDR3 termination, | ||
| - | | 2.0 V | FPGA Auxiliary I/O for memory high data rates((See the 7-Series FPGAs SelectIO Resources User Guide ([[http://www.xilinx.com/ | + | | 2.0 V | FPGA Auxiliary I/O for memory high data rates((See the 7-Series FPGAs SelectIO Resources User Guide ([[https://docs.xilinx.com/ |
| | VADJ (1.2-3.3 V) | User I/O, FMC and FPGA I/O | IC37: LTM4618 | | VADJ (1.2-3.3 V) | User I/O, FMC and FPGA I/O | IC37: LTM4618 | ||
| | 3.3 V | Audio analog supply | | 3.3 V | Audio analog supply | ||
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| The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience an importable UCF/XDC file is provided on the Digilent website to speed up the process. | The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience an importable UCF/XDC file is provided on the Digilent website to speed up the process. | ||
| - | For more details on the Xilinx memory interface solutions refer to the 7 Series FPGAs Memory Interface Solutions [[http://www.xilinx.com/ | + | For more details on the Xilinx memory interface solutions refer to the 7 Series FPGAs Memory Interface Solutions [[https://docs.xilinx.com/ |
| === 6.2. Quad-SPI Flash === | === 6.2. Quad-SPI Flash === | ||
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| The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. All signals in the SPI bus except SCK are general-purpose user I/O pins after FPGA configuration. SCK is an exception because it remains a dedicated pin even after configuration. Access to this pin is provided through a special FPGA primitive called STARTUPE2. The AXI Quad SPI IP core is recommended for easy access to the Flash memory. | The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. All signals in the SPI bus except SCK are general-purpose user I/O pins after FPGA configuration. SCK is an exception because it remains a dedicated pin even after configuration. Access to this pin is provided through a special FPGA primitive called STARTUPE2. The AXI Quad SPI IP core is recommended for easy access to the Flash memory. | ||
| - | **NOTE: Refer to the manufacturer’s [[http:// | + | **NOTE: Refer to the manufacturer’s [[http:// |
| {{ : | {{ : | ||
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| ==== 8. Oscillators/ | ==== 8. Oscillators/ | ||
| - | The Genesys 2 board includes several oscillators and crystals, of which two are connected to the FPGA. One differential LVDS 200MHz oscillator is connected to MRCC GPIO pins AD12/AD11 in bank 33. This input clock can drive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. Some rules restrict which MMCMs and PLLs may be driven by the 200MHz input clock. For a full description of these rules and of the capabilities of the Kintex-7 clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” ([[http://www.xilinx.com/ | + | The Genesys 2 board includes several oscillators and crystals, of which two are connected to the FPGA. One differential LVDS 200MHz oscillator is connected to MRCC GPIO pins AD12/AD11 in bank 33. This input clock can drive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. Some rules restrict which MMCMs and PLLs may be driven by the 200MHz input clock. For a full description of these rules and of the capabilities of the Kintex-7 clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” ([[https://docs.xilinx.com/ |
| Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy to use wrapper component around these clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Vivado Block Design or Core Generator tools. | Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy to use wrapper component around these clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Vivado Block Design or Core Generator tools. | ||
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| **NOTE:** The coupled routing and the anti-alias filters might limit the data speeds when used for digital signals. | **NOTE:** The coupled routing and the anti-alias filters might limit the data speeds when used for digital signals. | ||
| - | The XADC core within the Kintex-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the auxiliary analog input pairs connected to the JXADC header. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). This includes access to the temperature sensor and voltage monitors inside the FPGA. For more information on using the XADC core, refer to the Xilinx document titled “7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide” ([[http://www.xilinx.com/ | + | The XADC core within the Kintex-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the auxiliary analog input pairs connected to the JXADC header. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). This includes access to the temperature sensor and voltage monitors inside the FPGA. For more information on using the XADC core, refer to the Xilinx document titled “7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide” ([[https://docs.xilinx.com/ |
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| Each transceiver lane includes a receive pair and a transmit pair. Lanes DP0-DP3 are wired to quad 115. Lanes DP4-DP7 go to quad 116, along with the two reference clocks GBTCLK0 and GBTCLK1. The last two lanes DP8 and DP9 are connected to quad 117, while the rest of the pins in these three quads are left unused. | Each transceiver lane includes a receive pair and a transmit pair. Lanes DP0-DP3 are wired to quad 115. Lanes DP4-DP7 go to quad 116, along with the two reference clocks GBTCLK0 and GBTCLK1. The last two lanes DP8 and DP9 are connected to quad 117, while the rest of the pins in these three quads are left unused. | ||
| - | Since an MGTREFCLK can be routed to both the quad above and below its own, both reference clocks can be used to clock any channel in the three quads. Table 12, Table 13, and Table 14 show how the FMC gigabit signals are mapped to pins and GTX primitives. Refer to the 7 Series FPGAs GTX/GTH Transceivers User Guide ([[http://www.xilinx.com/ | + | Since an MGTREFCLK can be routed to both the quad above and below its own, both reference clocks can be used to clock any channel in the three quads. Table 12, Table 13, and Table 14 show how the FMC gigabit signals are mapped to pins and GTX primitives. Refer to the 7 Series FPGAs GTX/GTH Transceivers User Guide ([[https://docs.xilinx.com/ |
| //Table 12: Quad 115 pinout // | //Table 12: Quad 115 pinout // | ||