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programmable-logic:genesys-2:demos:oob [2022/09/12 15:38] – changed forum.digilentinc.com to forum.digilent.com jeff.greenberg_ni.comprogrammable-logic:genesys-2:demos:oob [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 +====== Genesys 2 Out of Box Demo ======
 +
 +{{:genesys2:genesys2-obl-1000.png?300|}}
 +
 +
 +===== Overview =====
 +
 +<WRAP round important 660px>
 +===Important.===
 +This project can only be programmed using Vivado/SDK 2015.4
 +</WRAP>
 +
 +==== Description ====
 +
 +The Genesys2 User Demo project demonstrates usage of most of the the Genesys2's peripheral devices.
 +. The behavior is as follows:
 + 
 +  * The 8 User LEDs are tied to the 8 User Switches. A back and forth animation is displayed on the LEDs.
 +  * The audio demo records a 5 second sample from microphone (J6) or line in (J7) and plays it back on headphone out (J4) or line out (J5). Record and playback is started by pushbuttons (described in the table below).
 +  * The Ethernet can be plugged into a network and is configured to work as an Echo Server.
 +  * With a DVI source connected to J9 (HDMI IN), the demo works as a pass-through buffer outputting the data on DVI output J8 (HDMI OUT) and also J10 (DISPLAYPORT OUT).
 +  * In the absence of a DVI source, the demo switches the video output to an internally generated pattern.
 +  * The XADC is set up to monitor the internal FPGA temperature, VCCINT voltage and VCCAUX voltage.
 +  * The on-board Oled shows the Digilent logo on power-up. After two seconds, it switches to display the XADC readings and the local IP address.
 +  * The Genesys2 also sends status messages through the UART terminal. It is configured to work at a baud rate of 115200 with 8 data bits, 1 stop bit, and no parity.
 +
 +Despite the fact that the version of the Out-of-Box demo that is programmed into the Genesys 2's flash during manufacturing correctly drives DisplayPort, due to changes made to the DisplayPort IP made between Vivado 2014.4 (the original version the demo was written in) and 2015.4 (targeted by the first GitHub release of the demo), DisplayPort is not supported by this demo.
 +
 +**Note:** //The source files for the original version of the Out-of-Box demo created for 2014.4, with a functioning DisplayPort implementation, were posted on the Digilent Forum here: [[https://forum.digilentinc.com/topic/19560-error-importing-genesys2-oob-project-sdk/#comment-53714]].//
 +==== Features Used ====
 +
 +|                                  ^ Not Used  ^ Used  ^
 +^ 8 user switches                  |           |   X   |
 +^ 8 user LEDs                      |           |   X   |
 +^ 128×32 monochrome Oled display   |           |   X   |
 +^ USB-UART Bridge                  |           |   X   |
 +^ 160-pin FMC LPC connector        |    X      |       |
 +^ Micro SD card connector          |    X      |       |
 +^ HDMI Sink and HDMI Source        |           |   X   |
 +^ DisplayPort Source               |           |   X   |
 +^ Audio codec w/ four 3.5mm jacks  |           |   X   |
 +^ 5 user push buttons              |           |   X   |
 +^ User EEPROM                      |    X      |       |
 +^ 10/100/1000 Ethernet PHY         |           |   X   |
 +^ 512MiB 800Mt/s DDR3 Memory       |           |   X   |
 +^ Serial Flash                     |    X      |       |
 +^ Four Pmod ports                  |    X      |       |
 +^ Pmod for XADC signals            |    X      |       |
 +^ USB HID Host                     |    X      |       |
 +
 +-------
 +===== Prerequisites =====
 +
 +===Hardware===
 +  * **Genesys2 FPGA board**
 +  * **Micro-USB cable**
 +  * **Genesys2 power supply**
 +  * **Various other cables**
 +
 +===Software===
 +  * **Xilinx SDK 2015.4** 
 +  * **Xilinx TEMAC IP Evaluation License**
 +  * **Xilinx Displayport IP Evaluation License**
 +  * **Digilent Board Support Files for Vivado** 
 +    * Follow the [[vivado:boardfiles|Vivado Board Files for Digilent 7-Series FPGA Boards]] guide on how to install Board Support Files for Vivado.
 +
 +-----
 +
 +===== Downloads =====
 +
 +Genesys2 Project Repository -- [[https://github.com/Digilent/Genesys-2-OOB/releases/download/v2015.4-1/Genesys-2-OOB-2015.4-1.zip|ZIP]] [[https://github.com/Digilent/Genesys-2-OOB|GIT Repo]]
 +
 +------
 +
 +===== How to... =====
 +
 +==== 1. Download the Project ====
 +
 +>1.1) Download the project zip file which can be downloaded above. Once you have downloaded the project, unzip it in the location of your choosing.
 +
 +>1.2) If you want to generate the project in Vivado, continue to step 2. If you want to move straight to Xilinx SDK, skip to step 5.
 +
 +==== 2. Generate the Project ====
 +>2.1) If not already installed, install the Vivado Board Files for the Genesys 2 by following this guide: [[vivado:boardfiles| Installing Vivado Board Files for Digilent Boards]].
 +
 +>2.2) Generate the **OOB** project by following this guide before continuing: [[vivado:github|How to Generate a Project from Digilent's Github]].
 +
 +==== 3. Build the Project ====
 +
 +>3.1) Click **Generate Bitstream** on the left hand menu towards the bottom. Vivado will run through both Run Synthesis and Run Implementation before it generates the bitstream automatically. 
 +>
 +>Note: If you want, you can click each step by itself in the order of **Run Synthesis**, **Run Implementation** and then **Generate Bitstream**.
 +>
 +>{{:basys3:buildflow.png?600|}}
 +
 +
 +==== 4. Export to SDK ====
 +
 +>4.1) Export the microblaze project by going to **File->Export->Export Hardware**. Click the check box to Include the bitstream, and export it local to project. This will create a .sdk folder in your project directory. Afterwards, click **File->Launch SDK**. Both the exported location and workspace should be left as <Local to Project>. Click "OK" to launch Xilinx SDK.
 +>
 +>4.2) Skip to step 6.
 +
 +==== 5. Open Xilinx SDK and create a workspace ====
 +
 +>5.1) Open up Xilinx SDK 2015.4 and create a workspace where your project will be saved.
 +>
 +>{{:genesys2:1.jpg?500|}}
 +
 +==== 6. Import the SDK files ====
 +
 +>6.1) In your project Explorer window on the left side, click **File->Import**, then under the general folder, select Existing projects. (Or just click **Import Project** on the main screen).
 +>
 +>{{:genesys2:2.jpg?500|}}
 +
 +>6.2) Navigate to where you saved the downloaded project, select the **sdk** folder, and click OK. In the //Import// window, click Finish to import the system hardware wrapper.
 +>
 +>{{:genesys2:3.jpg?300|}}
 +
 +>6.3) Import the projects by clicking //Finish//. You can ignore the warnings that may pop up.
 +>
 +>{{:genesys2:4.jpg?500|}}
 +
 +==== 7. Program the FPGA ====
 +
 +>7.1) Click **Xilinx Tools->Program FPGA** and click **Program**. Xilinx SDK will then program the FPGA with a microblaze bit file.
 +>
 +>{{:genesys2:5.jpg?500|}}
 +
 +==== 8. Program the Microblaze processor ====
 +
 +>8.1) Right click on the **demo** folder and click  **Run as->Launch on Hardware(GDB)**. The microblaze program will be programmed onto your Genesys 2.
 +>
 +>{{:genesys2:6.jpg?500|}}
 +
 +==== 9. Run the Project ====
 +
 +This portion will help you run the demo and observe all its features. **Note:** In its current state, the Ethernet port is not fully functional. 
 +
 +>9.1) Using the Switches with LEDs
 +>
 +>The Genesys2 will display a periodic light pattern once the program has started. Flipping any of the switches turns the corresponding LED on.
 +
 +>9.2) Setting up UART communications
 +>
 +>Plug a micro-USB cable into the plug labeled UART, and plug this into your computer.
 +>
 +>{{:genesys2:img_20151204_143237.jpg?300|}}
 +>
 +>You can use any serial terminal (Tera Term) to connect to the Genesys2 using 115200 baud rate, 8 data bits, no parity bit and 1 stop bit. Once connected, the Genesys2 will display the Internal temperature, VVCIN and VCCAUX voltage, as well as Ethernet information.
 +>
 +>{{:genesys2:7.jpg?500|}}
 +
 +>9.3) Oled Display
 +>
 +>Initially the Oled will display the internal temperature of the FPGA as well as the VCCINT and VCCAUX voltage. When BTNC is pressed, the Oled displays the current readings for VCC1V0, VCC1V5, and VCC1V8. When pressed again it shows the current readings from VCC3V3 and VCC5V0. The final page shows the MAC and IP address of the Genesys2.
 +>
 +>{{:genesys2:img_20151204_142807.jpg?300|}}{{:genesys2:img_20151204_142818.jpg?300|}}>{{:genesys2:img_20151204_142833.jpg?300|}}{{:genesys2:img_20151204_144516.jpg?300|}}
 +
 +>9.4) HDMI video
 +>
 +>Plugging an HDMI cord from HDMI OUT or DISPLAYPORT OUT to a monitor will show a generated video pattern shown below. If an HDMI input is plugged into HDMI IN, the video data will be passed through to the HDMI OUT and DISPLAYPORT OUT ports. A mouse can be plugged into 
 +>
 +>{{:nexys-video:img_20150701_142356.jpg?500|}}
 +
 +>9.5) Ethernet Echo Server
 +>
 +>Plugging the Genesys 2 into a router via an Ethernet cable to start up an echo server on a DHCP given IP address on the router. This can be accessed using a terminal program to connect to the IP address given by the DHCP server on port 7.
 +
 +>9.6) Audio Demo
 +>
 +>>9.6.1) Recording from an input
 +>>
 +>>To record from the microphone input, press bBTNU. To record from the line input, press BTNR. Once the recording is activated, the message "Start Recording..." will be sent over UART and the demo will record 5 seconds of audio. If any buttons are pressed during the recording, the message "Still Recording..." will be sent over UART.
 +>
 +>>9.6.2) Playing to an output
 +>>
 +>>To play to the microphone input, press BTND. To play to the line output, press BTNL. Once the playback is activated,  the message "Start Playback..." will be sent over UART and the demo will play 5 seconds of audio. If any buttons are pressed during the playback, the message "Still Playing..." will be sent over UART.
 +
 +>9.7) Image programmer project
 +>
 +>The imagedump project can be programmed onto your Genesys 2 just as you did the g2demo project. This demo provides a way to program a 1920x1080 image stored in a C header exported from GIMP to the flash of your board. This image can then be loaded into the VDMA and displayed using the g2demo project. With minimal modification, this project can be extended to dump the entire existing image out over UART, so that the contents can be validated.
 +
 +{{tag>learn programmable-logic genesys-2}}