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programmable-logic:eclypse-z7:reference-manual [2022/02/16 14:21] – change intro paragraph to remove the paragraph on software support, delegating that to the resource center. Arthur Brownprogrammable-logic:eclypse-z7:reference-manual [2022/10/04 04:38] (current) – external edit 127.0.0.1
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 Eclypse is designed to enable high speed analog data capture and analysis. It is a platform for research and rapid prototyping of test and measurement applications, potentially including software-defined radio, ultrasound, other medical devices, and much more. As a host board for [[zmod:start|Zmods]], applications for the Eclypse can vary significantly between system configurations. Eclypse is designed to enable high speed analog data capture and analysis. It is a platform for research and rapid prototyping of test and measurement applications, potentially including software-defined radio, ultrasound, other medical devices, and much more. As a host board for [[zmod:start|Zmods]], applications for the Eclypse can vary significantly between system configurations.
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 +=====%hide image_gallery=====
  
 {{Digilent Image Gallery  {{Digilent Image Gallery 
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 The PS consists of many components, including the Application Processing Unit (APU, which includes 2 Cortex-A9 processors), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory controller, and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins). Peripheral controllers that do not have their inputs and outputs connected to MIO pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers that are addressable in the processors’ memory space. The programmable logic is also connected to the interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain addressable control registers. Furthermore, cores implemented in the PL can trigger interrupts to the processors and perform DMA accesses to DDR3 memory. The PS consists of many components, including the Application Processing Unit (APU, which includes 2 Cortex-A9 processors), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory controller, and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins). Peripheral controllers that do not have their inputs and outputs connected to MIO pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers that are addressable in the processors’ memory space. The programmable logic is also connected to the interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain addressable control registers. Furthermore, cores implemented in the PL can trigger interrupts to the processors and perform DMA accesses to DDR3 memory.
  
-There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description, refer to the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]]. +There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description, refer to the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]]. 
  
 The tables in the dropdowns below depict the external components connected to the MIO pins of the Eclypse Z7. The Vivado board files found on the [[programmable-logic:eclypse-z7:start|Eclypse Z7 Resource Center]] can be used to properly configure the PS to work with these peripherals. It is also possible to use the example projects found on the resource center as a starting point for custom designs. The tables in the dropdowns below depict the external components connected to the MIO pins of the Eclypse Z7. The Vivado board files found on the [[programmable-logic:eclypse-z7:start|Eclypse Z7 Resource Center]] can be used to properly configure the PS to work with these peripherals. It is also possible to use the example projects found on the resource center as a starting point for custom designs.
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 ==Stage 2== ==Stage 2==
  
-The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple bare-metal “Hello World” application, to a Second Stage Boot loader used to boot an operating system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference Manual]].+The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple bare-metal “Hello World” application, to a Second Stage Boot loader used to boot an operating system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference Manual]].
  
 The Zynq Boot Image is created using Vivado and Xilinx Software Development Kit (Xilinx SDK). For information on creating this image please refer to the available Xilinx documentation for these tools. The Zynq Boot Image is created using Vivado and Xilinx Software Development Kit (Xilinx SDK). For information on creating this image please refer to the available Xilinx documentation for these tools.
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 Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specifically for the Eclypse Z7 memory interface PCB design. Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specifically for the Eclypse Z7 memory interface PCB design.
  
-For more details on memory controller operation, refer to the Xilinx [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+For more details on memory controller operation, refer to the Xilinx [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
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 ==== 4. Quad-SPI Flash ==== ==== 4. Quad-SPI Flash ====
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 The PS has a dedicated PLL capable of generating up to four reference clocks, each with settable frequencies, that can be used to clock custom logic implemented in the PL. Additionally, The Eclypse Z7 provides an external 125 MHz reference clock directly to pin D18 of the PL. The external reference clock allows the PL to be used completely independently of the PS, which can be useful for simple applications that do not require the processor. The PS has a dedicated PLL capable of generating up to four reference clocks, each with settable frequencies, that can be used to clock custom logic implemented in the PL. Additionally, The Eclypse Z7 provides an external 125 MHz reference clock directly to pin D18 of the PL. The external reference clock allows the PL to be used completely independently of the PS, which can be useful for simple applications that do not require the processor.
  
-The PL of the Zynq-Z7020 also includes four MMCM’s and four PLL’s that can be used to generate clocks with precise frequencies and phase relationships. Any of the four PS reference clocks or the 125 MHz external reference clock can be used as an input to the MMCMs and PLLs. For a full description of the capabilities of the Zynq PL clocking resources, refer to the [[https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf|7 Series FPGAs Clocking Resources User Guide]] available from Xilinx. +The PL of the Zynq-Z7020 also includes four MMCM’s and four PLL’s that can be used to generate clocks with precise frequencies and phase relationships. Any of the four PS reference clocks or the 125 MHz external reference clock can be used as an input to the MMCMs and PLLs. For a full description of the capabilities of the Zynq PL clocking resources, refer to the [[https://docs.xilinx.com/v/u/en-US/ug472_7Series_Clocking|7 Series FPGAs Clocking Resources User Guide]] available from Xilinx. 
  
 Xilinx offers the Clocking Wizard IP core to assist in integrating the MMCM's and PLL's into a design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy-to-use wrapper component around these clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Vivado and IP Integrator tools. Xilinx offers the Clocking Wizard IP core to assist in integrating the MMCM's and PLL's into a design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy-to-use wrapper component around these clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Vivado and IP Integrator tools.
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 The Eclypse Z7 provides several different methods of resetting the Zynq-7000 device, as described in the following sections: The Eclypse Z7 provides several different methods of resetting the Zynq-7000 device, as described in the following sections:
  
-=== 6.1. Power-on Reset ===+=== 6.1. Power-on Reset Signals ===
 The Zynq PS supports external power-on reset signals. The power-on reset is the master reset of the entire chip. This signal resets every register in the device capable of being reset. The Eclypse Z7 drives this signal from the VCC4V3 supply, the final non-adjustable supply to be brought up in the power-on sequence, in order to hold the system in reset until all power supplies are valid. A push-button, labeled BTNP, can be used to toggle the power-on reset signal. BTNP is located on the underside of the Eclypse Z7, below the SD card slot. The Zynq PS supports external power-on reset signals. The power-on reset is the master reset of the entire chip. This signal resets every register in the device capable of being reset. The Eclypse Z7 drives this signal from the VCC4V3 supply, the final non-adjustable supply to be brought up in the power-on sequence, in order to hold the system in reset until all power supplies are valid. A push-button, labeled BTNP, can be used to toggle the power-on reset signal. BTNP is located on the underside of the Eclypse Z7, below the SD card slot.
  
-==== 6.2. Processor Subsystem Reset ====+=== 6.2. Processor Subsystem Reset ===
  
 The external system reset button, labeled BTNR, resets the Zynq device without disturbing the debug environment. For example, the previous break points set by the user remain valid after system reset. Due to security concerns, system reset erases all memory content within the PS, including the On-Chip-Memory (OCM). The PL is also cleared during a system reset. System reset does not cause the boot mode strapping pins to be re-sampled. After changing the boot mode jumper a power cycle is needed to act on the new setting. BTNR is located on the underside of the Eclypse Z7, below the SD card slot. The external system reset button, labeled BTNR, resets the Zynq device without disturbing the debug environment. For example, the previous break points set by the user remain valid after system reset. Due to security concerns, system reset erases all memory content within the PS, including the On-Chip-Memory (OCM). The PL is also cleared during a system reset. System reset does not cause the boot mode strapping pins to be re-sampled. After changing the boot mode jumper a power cycle is needed to act on the new setting. BTNR is located on the underside of the Eclypse Z7, below the SD card slot.
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 ==== 9. microSD Slot ==== ==== 9. microSD Slot ====
  
-The Eclypse Z7 provides a microSD slot (J4) for non-volatile external memory storage as well as booting the Zynq. The slot is wired to Bank 1/501 MIO[40-45], and also includes a card detect signal attached to MIO 47. On the PS side, peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 9.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference Manual]], SDIO host mode is the only mode supported.+The Eclypse Z7 provides a microSD slot (J4) for non-volatile external memory storage as well as booting the Zynq. The slot is wired to Bank 1/501 MIO[40-45], and also includes a card detect signal attached to MIO 47. On the PS side, peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 9.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference Manual]], SDIO host mode is the only mode supported.
  
 //Table 9.1: microSD pinout// //Table 9.1: microSD pinout//