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| programmable-logic:eclypse-z7:reference-manual [2021/05/14 16:04] – ↷ Page moved from reference:programmable-logic:eclypse-z7:reference-manual to programmable-logic:eclypse-z7:reference-manual Arthur Brown | programmable-logic:eclypse-z7:reference-manual [2022/10/04 04:38] (current) – external edit 127.0.0.1 | ||
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| ====== Eclypse Z7 Hardware Reference Manual ====== | ====== Eclypse Z7 Hardware Reference Manual ====== | ||
| - | The Eclypse Z7 is a powerful prototyping platform, featuring Xilinx' | + | The Eclypse Z7 is a powerful prototyping platform, featuring Xilinx' |
| - | Eclypse is designed to enable high speed analog data capture and analysis | + | Eclypse is designed to enable high speed analog data capture and analysis. It is a platform for research and rapid prototyping of test and measurement applications, |
| - | Petalinux is supported out of the box. Pre-built Linux images are accompanied by a software < | + | =====%hide image_gallery===== |
| {{Digilent Image Gallery | {{Digilent Image Gallery | ||
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| * USB micro AB port with USB 2.0 PHY with Host/ | * USB micro AB port with USB 2.0 PHY with Host/ | ||
| * **Zmod Ports** | * **Zmod Ports** | ||
| - | * 2 ports following the SYZYGY Standard interface specification | + | * 2 ports following the SYZYGY™ Standard interface specification |
| - | * Compatible with a variety of SYZYGY pods, allowing for a wide variety of applications | + | * Compatible with a variety of SYZYGY™ pods, allowing for a wide variety of applications |
| * Dedicated differential clocks for input and output | * Dedicated differential clocks for input and output | ||
| * 8 differential I/Os per port | * 8 differential I/Os per port | ||
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| ^ Callout # ^ Description ^ Callout # ^ Description ^ Callout # ^ Description ^ | ^ Callout # ^ Description ^ Callout # ^ Description ^ Callout # ^ Description ^ | ||
| - | | 1 | Board Indicator LEDs (LD4) | 7 | SYZYGY Ports | 13 | Reset Buttons (underside of board) | | + | | 1 | Board Indicator LEDs (LD4) | 7 | SYZYGY™ Ports | 13 | Reset Buttons (underside of board) | |
| | 2 | Header for Case Power Switch | 8 | Pmod Ports | 14 | microSD Card Slot | | | 2 | Header for Case Power Switch | 8 | Pmod Ports | 14 | microSD Card Slot | | ||
| | 3 | Power Switch | | 3 | Power Switch | ||
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| An Eclypse Z7 Enclosure Kit may optionally be added on, which provides a sturdy case for the Eclypse platform. The Enclosure Kit includes a case fan for additional cooling, and exposes the connectors of loaded Zmod ADCs and DACs, as well as the Eclypse Z7's Pmod expansion connectors, power switch, status LEDs, and more. | An Eclypse Z7 Enclosure Kit may optionally be added on, which provides a sturdy case for the Eclypse platform. The Enclosure Kit includes a case fan for additional cooling, and exposes the connectors of loaded Zmod ADCs and DACs, as well as the Eclypse Z7's Pmod expansion connectors, power switch, status LEDs, and more. | ||
| - | For more information on purchasing an Eclypse Z7, see the [[https://store.digilentinc.com/ | + | For more information on purchasing an Eclypse Z7, see the [[https://digilent.com/shop/ |
| - | [[zmod: | + | [[zmod: |
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| Digilent currently does not provide hardware platforms or examples for Xilinx' | Digilent currently does not provide hardware platforms or examples for Xilinx' | ||
| - | Design resources, example projects, and tutorials are available for download at the [[reference: | + | Design resources, example projects, and tutorials are available for download at the [[start|Eclypse Z7 Resource Center]]. |
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| The PS consists of many components, including the Application Processing Unit (APU, which includes 2 Cortex-A9 processors), | The PS consists of many components, including the Application Processing Unit (APU, which includes 2 Cortex-A9 processors), | ||
| - | There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description, | + | There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description, |
| - | The tables in the dropdowns below depict the external components connected to the MIO pins of the Eclypse Z7. The Vivado board files found on the [[reference:programmable-logic: | + | The tables in the dropdowns below depict the external components connected to the MIO pins of the Eclypse Z7. The Vivado board files found on the [[programmable-logic: |
| --> MIO 0-15 : Bank 500 # | --> MIO 0-15 : Bank 500 # | ||
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| | VADJC | VIN12V0 | | VADJC | VIN12V0 | ||
| - | The power budget of VCC5V0 is shared by the SYZYGY ports, USB OTG VBUS, RGB LEDs, and Case Fan. As such, the actual maximum current achievable by each peripheral varies with the Eclypse Z7's system configuration. Under worst-case conditions, VCC5V0 is capable of outputting a minimum of 3A of continuous current. In this scenario, 1A is budgeted for each Zmod | + | The power budget of VCC5V0 is shared by the SYZYGY™ ports, USB OTG VBUS, RGB LEDs, and Case Fan. As such, the actual maximum current achievable by each peripheral varies with the Eclypse Z7's system configuration. Under worst-case conditions, VCC5V0 is capable of outputting a minimum of 3A of continuous current. In this scenario, 1A is budgeted for each Zmod |
| - | The Platform MCU (PMCU) enumerates the SYZYGY ports and determines the power needs of each Zmod installed in the system. The 5V power budget of the Eclypse is then determined based on the needs of each Zmod, as well as the USB OTG VBUS, RGB LEDs, and Fan. Table 1.2.2 describes the 5V power budget of the Eclypse Z7 in more detail. | + | The Platform MCU (PMCU) enumerates the SYZYGY™ ports and determines the power needs of each Zmod installed in the system. The 5V power budget of the Eclypse is then determined based on the needs of each Zmod, as well as the USB OTG VBUS, RGB LEDs, and Fan. Table 1.2.2 describes the 5V power budget of the Eclypse Z7 in more detail. |
| //Table 1.2.2: Eclypse 5V Power Budget// | //Table 1.2.2: Eclypse 5V Power Budget// | ||
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| | Case Fan | 250 | | | Case Fan | 250 | | ||
| - | The two SYZYGY ports share a budget of 2A from the 3.3V supply. The two Pmod ports share a budget of 0.5A, which is allocated to the SYZYGY ports if no Pmods are installed. | + | The two SYZYGY™ ports share a budget of 2A from the 3.3V supply. The two Pmod ports share a budget of 0.5A, which is allocated to the SYZYGY™ ports if no Pmods are installed. |
| Due to the requirements of the custom power sequencer (IC29), Digilent recommends that peripheral modules (Pmods and Zmods) attached to and powered by the Eclypse meet the specifications described in Table 1.2.3. | Due to the requirements of the custom power sequencer (IC29), Digilent recommends that peripheral modules (Pmods and Zmods) attached to and powered by the Eclypse meet the specifications described in Table 1.2.3. | ||
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| === 1.5. Case Fan === | === 1.5. Case Fan === | ||
| - | In addition to the FPGA fan, the Eclypse Z7 can power a Case Fan, connected to the board via fan header J14 (labeled " | + | In addition to the FPGA fan, the Eclypse Z7 can power a Case Fan, connected to the board via fan header J14 (labeled " |
| === 1.6. Platform MCU === | === 1.6. Platform MCU === | ||
| - | As noted in previous sections, the Eclypse Z7 uses an Atmega328PB microcontroller (IC10), referred to as the Platform MCU (PMCU), to implement the SmartVIO requirements of the SYZYGY standard, as well as to monitor the Zynq die temperature, | + | As noted in previous sections, the Eclypse Z7 uses an Atmega328PB microcontroller (IC10), referred to as the Platform MCU (PMCU), to implement the SmartVIO requirements of the SYZYGY™ standard, as well as to monitor the Zynq die temperature, |
| - | When the Eclypse is turned on, the PMCU enumerates the pods attached to the Eclypse' | + | When the Eclypse is turned on, the PMCU enumerates the pods attached to the Eclypse' |
| - | After SYZYGY enumeration is complete, the PMCU configures itself as an I2C slave device with a chip address of 0x60. Control of the I2C bus is then handed over to the Zynq's I2C 1 peripheral (MIO[12: | + | After SYZYGY™ enumeration is complete, the PMCU configures itself as an I2C slave device with a chip address of 0x60. Control of the I2C bus is then handed over to the Zynq's I2C 1 peripheral (MIO[12: |
| The following tables describe the features of the Platform MCU supported by the Eclypse Z7: | The following tables describe the features of the Platform MCU supported by the Eclypse Z7: | ||
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| ==Stage 2== | ==Stage 2== | ||
| - | The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple bare-metal “Hello World” application, | + | The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple bare-metal “Hello World” application, |
| The Zynq Boot Image is created using Vivado and Xilinx Software Development Kit (Xilinx SDK). For information on creating this image please refer to the available Xilinx documentation for these tools. | The Zynq Boot Image is created using Vivado and Xilinx Software Development Kit (Xilinx SDK). For information on creating this image please refer to the available Xilinx documentation for these tools. | ||
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| Both the memory chips and the PS DDR bank are powered from the 1.35V supply. The mid-point reference of 0.675V is created with a simple resistor divider and is available to the Zynq as an external reference. | Both the memory chips and the PS DDR bank are powered from the 1.35V supply. The mid-point reference of 0.675V is created with a simple resistor divider and is available to the Zynq as an external reference. | ||
| - | For proper operation, it is essential that the PS memory controller is configured properly. Settings range from the actual memory flavor to the board trace delays. For your convenience, | + | For proper operation, it is essential that the PS memory controller is configured properly. Settings range from the actual memory flavor to the board trace delays. For your convenience, |
| For best DDR3L performance, | For best DDR3L performance, | ||
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| Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specifically for the Eclypse Z7 memory interface PCB design. | Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specifically for the Eclypse Z7 memory interface PCB design. | ||
| - | For more details on memory controller operation, refer to the Xilinx [[http://www.xilinx.com/ | + | For more details on memory controller operation, refer to the Xilinx [[https://docs.xilinx.com/ |
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| ==== 4. Quad-SPI Flash ==== | ==== 4. Quad-SPI Flash ==== | ||
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| ==== 5. Oscillators/ | ==== 5. Oscillators/ | ||
| - | The Eclypse Z7 provides a 33.3333 < | + | The Eclypse Z7 provides a 33.3333 < |
| The PS has a dedicated PLL capable of generating up to four reference clocks, each with settable frequencies, | The PS has a dedicated PLL capable of generating up to four reference clocks, each with settable frequencies, | ||
| - | The PL of the Zynq-Z7020 also includes four MMCM’s and four PLL’s that can be used to generate clocks with precise frequencies and phase relationships. Any of the four PS reference clocks or the 125 MHz external reference clock can be used as an input to the MMCMs and PLLs. For a full description of the capabilities of the Zynq PL clocking resources, refer to the [[https://www.xilinx.com/ | + | The PL of the Zynq-Z7020 also includes four MMCM’s and four PLL’s that can be used to generate clocks with precise frequencies and phase relationships. Any of the four PS reference clocks or the 125 MHz external reference clock can be used as an input to the MMCMs and PLLs. For a full description of the capabilities of the Zynq PL clocking resources, refer to the [[https://docs.xilinx.com/ |
| Xilinx offers the Clocking Wizard IP core to assist in integrating the MMCM's and PLL's into a design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy-to-use wrapper component around these clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Vivado and IP Integrator tools. | Xilinx offers the Clocking Wizard IP core to assist in integrating the MMCM's and PLL's into a design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy-to-use wrapper component around these clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Vivado and IP Integrator tools. | ||
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| The Eclypse Z7 provides several different methods of resetting the Zynq-7000 device, as described in the following sections: | The Eclypse Z7 provides several different methods of resetting the Zynq-7000 device, as described in the following sections: | ||
| - | === 6.1. Power-on Reset === | + | === 6.1. Power-on Reset Signals |
| The Zynq PS supports external power-on reset signals. The power-on reset is the master reset of the entire chip. This signal resets every register in the device capable of being reset. The Eclypse Z7 drives this signal from the VCC4V3 supply, the final non-adjustable supply to be brought up in the power-on sequence, in order to hold the system in reset until all power supplies are valid. A push-button, | The Zynq PS supports external power-on reset signals. The power-on reset is the master reset of the entire chip. This signal resets every register in the device capable of being reset. The Eclypse Z7 drives this signal from the VCC4V3 supply, the final non-adjustable supply to be brought up in the power-on sequence, in order to hold the system in reset until all power supplies are valid. A push-button, | ||
| - | ==== 6.2. Processor Subsystem Reset ==== | + | === 6.2. Processor Subsystem Reset === |
| The external system reset button, labeled BTNR, resets the Zynq device without disturbing the debug environment. For example, the previous break points set by the user remain valid after system reset. Due to security concerns, system reset erases all memory content within the PS, including the On-Chip-Memory (OCM). The PL is also cleared during a system reset. System reset does not cause the boot mode strapping pins to be re-sampled. After changing the boot mode jumper a power cycle is needed to act on the new setting. BTNR is located on the underside of the Eclypse Z7, below the SD card slot. | The external system reset button, labeled BTNR, resets the Zynq device without disturbing the debug environment. For example, the previous break points set by the user remain valid after system reset. Due to security concerns, system reset erases all memory content within the PS, including the On-Chip-Memory (OCM). The PL is also cleared during a system reset. System reset does not cause the boot mode strapping pins to be re-sampled. After changing the boot mode jumper a power cycle is needed to act on the new setting. BTNR is located on the underside of the Eclypse Z7, below the SD card slot. | ||
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| The Eclypse Z7 includes an FTDI FT2232HQ USB-UART bridge (attached to connector J6) that lets PC applications communicate with the board using standard COM port commands (or the tty interface in Linux). Drivers are automatically installed in Windows and newer versions of Linux when the Eclypse Z7 is attached. Serial port data is exchanged with the Zynq using a two-wire serial port (TXD/RXD). After the drivers are installed, I/O commands can be used from the PC directed to the COM port to produce serial data traffic on the Zynq pins. The port is tied to PS (MIO) pins and can be used in combination with the UART 0 controller. | The Eclypse Z7 includes an FTDI FT2232HQ USB-UART bridge (attached to connector J6) that lets PC applications communicate with the board using standard COM port commands (or the tty interface in Linux). Drivers are automatically installed in Windows and newer versions of Linux when the Eclypse Z7 is attached. Serial port data is exchanged with the Zynq using a two-wire serial port (TXD/RXD). After the drivers are installed, I/O commands can be used from the PC directed to the COM port to produce serial data traffic on the Zynq pins. The port is tied to PS (MIO) pins and can be used in combination with the UART 0 controller. | ||
| - | The Zynq presets file (available in the [[reference:programmable-logic: | + | The Zynq presets file (available in the [[programmable-logic: |
| Two status LEDs provide visual feedback on traffic flowing through the port: the transmit LED (the lower of the two yellow LEDs in the circuit board indicator, LD4) and the receive LED (the upper of the two yellow LEDs in the circuit board indicator, LD4). Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC. | Two status LEDs provide visual feedback on traffic flowing through the port: the transmit LED (the lower of the two yellow LEDs in the circuit board indicator, LD4) and the receive LED (the upper of the two yellow LEDs in the circuit board indicator, LD4). Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC. | ||
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| ==== 8. Zmod Ports ==== | ==== 8. Zmod Ports ==== | ||
| - | The Eclypse Z7 features two Zmod ports, which use SYZYGY Standard interfaces to communicate with installed SYZYGY pods. Both ports are compatible with version 1.1 of the SYZYGY specification from Opal Kelly. | + | The Eclypse Z7 features two Zmod ports, which use SYZYGY™ Standard interfaces to communicate with installed SYZYGY™ pods. Both ports are compatible with version 1.1 of the SYZYGY™ specification from Opal Kelly. |
| - | SYZYGY SmartVIO functionality is implemented by the Eclypse' | + | SYZYGY™ SmartVIO functionality is implemented by the Eclypse' |
| - | **Warning**: | + | **Warning**: |
| - | Each SYZYGY Standard interface contains 16 single-ended I/O pins, 8 differential I/O pairs (which can alternatively be used as 16 additional single-ended I/O pins), and two dedicated differential clocks - one for input and one for output. Each Zmod port has a I/O bank of the Zynq dedicated to it, which is powered by a dedicated adjustable rail, configured by the Platform MCU as the Eclypse is powered on. Template constraints for each Zmod port can be found in the Eclypse Z7's Master XDC file, available through Digilent' | + | Each SYZYGY™ Standard interface contains 16 single-ended I/O pins, 8 differential I/O pairs (which can alternatively be used as 16 additional single-ended I/O pins), and two dedicated differential clocks - one for input and one for output. Each Zmod port has a I/O bank of the Zynq dedicated to it, which is powered by a dedicated adjustable rail, configured by the Platform MCU as the Eclypse is powered on. Template constraints for each Zmod port can be found in the Eclypse Z7's Master XDC file, available through Digilent' |
| Digilent provides Eclypse-compatible low-level IPs, scripted Vivado flows, and software libraries to support each [[zmod: | Digilent provides Eclypse-compatible low-level IPs, scripted Vivado flows, and software libraries to support each [[zmod: | ||
| - | For more information on the SYZYGY standard, see [[https:// | + | For more information on the SYZYGY™ standard, see [[https:// |
| - | === 8.1. SYZYGY Pod Compatibility === | + | === 8.1. SYZYGY™ Pod Compatibility === |
| - | The Eclypse' | + | The Eclypse' |
| - | //Table 8.1.1: SYZYGY Compatibility Table// | + | //Table 8.1.1: SYZYGY™ Compatibility Table// |
| ^ Parameter | ^ Parameter | ||
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| ==== 9. microSD Slot ==== | ==== 9. microSD Slot ==== | ||
| - | The Eclypse Z7 provides a microSD slot (J4) for non-volatile external memory storage as well as booting the Zynq. The slot is wired to Bank 1/501 MIO[40-45], and also includes a card detect signal attached to MIO 47. On the PS side, peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 9.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[http://www.xilinx.com/ | + | The Eclypse Z7 provides a microSD slot (J4) for non-volatile external memory storage as well as booting the Zynq. The slot is wired to Bank 1/501 MIO[40-45], and also includes a card detect signal attached to MIO 47. On the PS side, peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 9.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[https://docs.xilinx.com/ |
| //Table 9.1: microSD pinout// | //Table 9.1: microSD pinout// | ||
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| | **SD_CD** | | **SD_CD** | ||
| - | The SD slot is powered from 3.3V, but is connected through MIO Bank 1/501 (1.8V). Therefore, a TI TXS02612 level shifter performs this translation. The TXS02612 is actually a 2-port SDIO port expander, but only its level shifter function is used. The connection diagram can be seen on Figure 9.1. Mapping out the correct pins and configuring the interface is handled by the Eclypse Z7 board files, available on the [[reference: | + | The SD slot is powered from 3.3V, but is connected through MIO Bank 1/501 (1.8V). Therefore, a TI TXS02612 level shifter performs this translation. The TXS02612 is actually a 2-port SDIO port expander, but only its level shifter function is used. The connection diagram can be seen on Figure 9.1. Mapping out the correct pins and configuring the interface is handled by the Eclypse Z7 board files, available on the [[start|Eclypse Z7 Resource Center]]. |
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